tmr

Generic Interface to Teensy Timers

Safe, self-healing bare-metal x86-64 operating system designed for radiation-hardened aerospace systems.

TMR utilities for the SpyDrNet project

REM/TMR/TLR engine for Muse S Athena (Konkoly-like protocol)

Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.

This example demonstrates how to emulate a Modbus host for communicating with client over RS485 communication and UART peripheral using PIC microcontroller. Compatible PIC16F152xx family of MCUs are PIC16F15214,PIC16F15223,PIC16F15254,PIC16F15276

Spring 2020 Senior Project

Time-frequency power and inter-trial phase consistency (ITPC) analysis of EEG responses to Targeted Memory Reactivation (TMR) stimuli during N3 sleep.

🚁 Fault-Tolerant Autonomous Drone Navigation System using Java TMR (Triple Modular Redundancy)

This code example demonstrates how to realize a SPI-RS485 bridge and Modbus client using built-in MSSP (SPI mode) and UART peripherals of the PIC microcontroller. Compatible PIC16F152xx family of MCUs are PIC16F15214,PIC16F15223,PIC16F15244,PIC16F15254

This repository provides a MCC-generated code example for using TMR0 in 16-bit Mode with sleep operation. An interrupt will wake up the device every 10s and LED0 will light up for 100 ms and then the MCU will be put back to sleep.

Radar DSP SIMULATION :: I/Q generation → Windowing → FFT/PSD → CA-CFAR → TMR majority vote → Doppler/velocity estimation → Tracker (SEARCH/LOCKED) → Kalman filter → Watchdog | SIM - Not Real hardware.

Synthesizable 3-stage pipelined RV32E RISC-V processor core in SystemVerilog-2012 for Artix-7 FPGA (Nexys 4) and ASIC. Features hazard forwarding, 32KB BRAM, MMIO LED peripherals, 100% RISC-V ACT 4.0 compliance (195/195 tests passed), live silicon validation, and ongoing ECC SEC-DED fault-tolerance & Cadence Genus ASIC synthesis extensions.

A criticality-aware H.264 encoder simulation that models how different encoding blocks can be protected with resilience strategies such as retries, ECC, TMR, and checkpointing. This project demonstrates how fault-tolerant design principles can be applied to video compression pipelines.

ControlX is a C-based framework for sensor data processing and control in spacecraft systems.

Project is a PIC16F18076 beginners guide to entering and exiting the device's sleep mode and a high level discussion on low-power techniques. It uses the PIC16F18076 Curiosity Nano and MPLAB X/MCC.

This code example demonstrates several solutions for calculating the pulse width and duty cycle from a signal. Compatibly PIC16F180xx family MCUs are: PIC16F18076

TMR-based hardware Trojan detection with cycle-accurate temporal monitor — deployed on Lattice iCE40 FPGA

Bilingual technical review of MRAM technology, covering memory hierarchies, MTJ/TMR physics, STT-MRAM, SOT-MRAM, applications, engineering challenges, and future directions.

Space-grade UART controller designed in VHDL. Implements radiation mitigation techniques (TMR, Self-Scrubbing) compliant with ECSS standards, verified through SEU fault injection using CocoTB.