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OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated Dec 26, 2025
Verilog

AUCOHL / DFFRAM

Star

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Nov 10, 2025
Verilog

purdue-onchip / gds2Para

Star

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Apr 23, 2023
C++

OpenTimer / Parser-Verilog

Star

A Standalone Structural Verilog Parser

flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc

Updated Mar 31, 2022
Verilog

luckyrantanplan / nthu-route

Star

VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Feb 15, 2026
C++

imsanjoykb / Electrical-And-Electronic-Engineering-Course-Materials

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Electrical And Electronic Engineering Course Materials

course-materials fabrication vlsi electrical-engineering biomedical-engineering electronics-engineering vlsi-circuits control-systems-engineering power-system handnote vlsi-course solid-state-device eee-semester-course eee-ourse power-syetem-protection circute-design-course

Updated Mar 22, 2022
MATLAB

ehw-fit / evoapproxlib

Star

Library of approximate arithmetic circuits

fpga arithmetic approximate-computing vlsi-circuits

Updated Jan 14, 2026
Verilog

OpenTimer / Parser-SPEF

Star

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Aug 7, 2022
C++

mihir8181 / VLSI-Design-Digital-System

Star

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Updated Mar 22, 2019

srohit0 / mida

Sponsor

Star

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

machine-learning deep-neural-networks deep-learning neural-network machine-learning-algorithms artificial-intelligence artificial-neural-networks logistic-regression feedforward-neural-network polynomial-regression vlsi machine-intelligence design-automation electronic-design-automation vlsi-circuits vlsi-design vlsi-machine-learning vlsi-deep-learning

Updated Dec 9, 2018
Jupyter Notebook

SubZer0811 / VLSI

Star

All the projects and assignments done as part of VLSI course.

magic verilog vlsi wallace-tree-multiplier cmos vlsi-circuits recursive-doubling-cla ripple-carry-adder universal-shift-register

Updated Sep 23, 2020
Verilog

levibyte / pyqt_genetic_algo

Star

genetic algorithm usage for routing optimization ( pyqt )

qt mvc optimization genetic-algorithm routing eda routing-engine pyqt vlsi placement placement-engine placements vlsi-circuits

Updated Mar 24, 2019
Python

paripath / cdf

Star

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

characterization power-analysis hspice spice-simulator vlsi-circuits timing-analysis vlsi-design vlsi-cad

Updated Feb 13, 2020
C++

DuttPanchal04 / cmos-logic-gates-layout-design-electric-vlsi

Star

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.

simulation vlsi vlsi-physical-design cmos digital-design vlsi-circuits vlsi-design cmos-inverter cmos-circuits layout-design cmos-logic schematic-design drc-check electric-vlsi-free-tool

Updated May 10, 2025

tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier

Star

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

digital verilog vlsi verilog-hdl multiplier hardware-description-language vlsi-circuits baugh-wooley digitalelectronics

Updated Jun 1, 2021
Verilog

ali-ece / Design-of-optimal-CMOS-ring-oscillator-using-an-intelligent-optimization-tool

Star

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect trad…