cadence-innovus

ASIC Physical Design of FIFO using Cadence Innovus | Floorplan → CTS → Routing → Timing & Power Analysis

Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

Synthesizable 3-stage pipelined RV32E RISC-V processor core in SystemVerilog-2012 for Artix-7 FPGA (Nexys 4) and ASIC. Features hazard forwarding, 32KB BRAM, MMIO LED peripherals, 100% RISC-V ACT 4.0 compliance (195/195 tests passed), live silicon validation, and ongoing ECC SEC-DED fault-tolerance & Cadence Genus ASIC synthesis extensions.

Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.

Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).

Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.

32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.

The development of SOC for BLDC motor control (designed from RTL to GDSII)

Mini Stereo Digital Audio Processor | ASAP7 7nm ASIC design | Stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus physical implementation, and verification documentation.

LLM-powered CLI that generates Cadence Innovus TCL scripts from natural-language IC design tasks. Built on the Anthropic API with retrieval over EDA documentation.

全國大學校院積體電路設計競賽 實作練習

Method study of a VLSI chip-stitch boundary search (UCLA ECE 201A): enumerates its cost and subset coverage, and shows the objective prefers a layer subset the search structurally cannot reach. Python stdlib only, no EDA tools.

Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.