Convert ethernet/RoCEv2 to pure VHDL, removing all generated Verilog and the 36 CRC table files

[ruck314]

Motivation

PR #1465 bundles three changes into one merge: the Verilog to VHDL port, a functional rewrite (responder path, RDMA READ, multi queue pair), and a redesigned AXI-Lite map that breaks downstream PyRogue integrations. With the Verilog deleted there is no golden reference to attribute a failure to, and its validation suite lives outside surf, so surf CI gains no regression coverage.

This PR does only the port, bit-exact and register-compatible, and adds the cocotb suite surf was missing. Optimization comes after this PR, once the port has established a verified baseline to measure against: with one KCU105 and a full build per iteration.

Description

Convert ethernet/RoCEv2 from mixed Verilog/VHDL to pure VHDL. All 18 Bluespec-compiler-generated Verilog files and all 36 crc_tab_*.mem lookup tables are deleted, so the whole RoCEv2 stack can now be simulated with GHDL and cocotb, which was impossible while any Verilog remained because the apt ghdl build has no mixed-language support. Resource use drops on the RoCEv2_10GbeRudpKcu105Example build (LUT 88679 to 81168, FF 126004 to 113840, BRAM tiles 217 to 279.5 as the CRC tables move from LUT ROM into block RAM), timing closes with no failing endpoints, and the converted design has been validated on a KCU105.

Details

• Hand-writes the 13 blue-lib Bluespec runtime primitives in VHDL rather than transpiling them, because CRegN5 intra-cycle read-after-write ordering and RWire valid-bit semantics need human judgment.
• Translates the three generated blue-rdma modules to VHDL, each verified byte-regenerable from its unmodified Verilog source and compared cycle by cycle against it with zero mismatches before that source was deleted.
• Replaces blue-crc outright with a native RoCEv2ICrc built on surf.CrcPkg, generating its lookup tables at elaboration from a deferred constant instead of reading the 36 .mem files. Send side drops from 6569 LUT / 7342 FF to 2147 LUT / 690 FF, receive side from 6582 LUT / 7170 FF to 2183 LUT / 705 FF.
• Binds the translated transport layer into RoCEv2Engine.vhd as a direct VHDL entity, so the RDMA datapath is all-VHDL from the engine down.
• Loads ethernet/RoCEv2 in ethernet/ruckus.tcl's non-Vivado branch, the one Ethernet subdirectory whose whole dependency closure is reachable without Vivado, so all 37 sources reach the GHDL import farm and make analysis covers them on every run.
• Adds cocotb coverage for the AXI-Lite configurator, DCQCN rate control, the resize/endian-swap stage, both iCRC pipeline stages, the iCRC engine in both directions, all 9,216 entries of the generated CRC table constant, the RDMA core, and the assembled RoCEv2AxiStreamRdma top level, whose directed-write case walks a queue pair from RESET to RTS and checks the resulting frame field by field against a spec-derived reference.
• Retires the record/replay equivalence harness that established the blue-rdma translations, along with roughly 1 MB of committed vectors, since it recorded from Verilog sources this change deletes and CI never installed iverilog to record with. blue-rdma/README.md keeps its conversion-time findings as history, separate from what runs on every push.
• Excludes mkQP.vhd and mkTransportLayer.vhd from VSG, since both are regenerated rather than edited and exceed the file-length and line-length rules. They were the only two files in the repository reporting either rule.

Validation performed:

• make MODULES="$PWD" analysis exited 0, analyzing 533 files including all 37 under ethernet/RoCEv2.
• Full cocotb regression passed with CI's own invocation, pytest -n auto --dist=worksteal tests: 936 passed, 21 skipped, no failures. The skips are pre-existing and outside the changed directories.
• tests/ethernet/RoCEv2 passed 32 items with no skips, 14 of them launching a GHDL simulation.
• VSG reported no violations.
• Flake8 passed for the changed Python.
• Fifteen rocev2PrbsTest.py runs on a KCU105 across three configurations all exited 0 with a PASS verdict and zero receive errors.