Remove the remaining non-RoCEv2 Verilog from surf

[ruck314]

Description

Removes the Verilog and SystemVerilog that #1468 does not cover, so that after both changes land the only non-VHDL sources left in surf are protocols/i2c/rtl and simlink. Deletes both Micron DDR vendor simulation models (devices/Micron/ddr3 and devices/Micron/ddr4), the unused SaciSlaveAnalog.v simulation model, and the four generated UdpDebugBridge_stub.v synthesis stubs.

Downstream impact: projects whose testbenches include ddr3.v or arch_package.sv from surf/devices/Micron/ddr3/tb or ddr4/tb must vendor those Micron models locally.

Details

• Both Micron DDR models are removed in full rather than by file extension. arch_package.sv includes arch_defines.v, and the four *_ddr3_parameters.vh headers exist only to be included by ddr3.v, so deleting just the .v files would leave two non-functional vendor models. devices/Micron/ruckus.tcl drops the two now-dangling loadRuckusTcl lines; mt28ew, n25q, and p30 are unchanged. The per-device manifests that carried the Verilog-specific USED_IN {implementation} and FILE_TYPE {Verilog Header} properties go with their directories, so nothing is left to patch.
• protocols/saci/saci1/sim/SaciSlaveAnalog.v had no instantiation anywhere in the repository. It reached builds only through the loadSource -sim_only -dir glob over protocols/saci/saci1/sim, so no manifest change is needed. The remaining VHDL in that directory is untouched.
• The four xilinx/xvc-udp/dcp/{7Series,UltraScale}/{Impl,Stub}/images/UdpDebugBridge_stub.v files are Vivado synth-stub byproducts that no manifest loads. xilinx/xvc-udp/ruckus.tcl loads only UdpDebugBridge.dcp, and the two DCP-regeneration manifests load only dcp/core/*.vhd. The sibling UdpDebugBridge_stub.vhd and .vho reference files are kept, since they document the black-box port list without reintroducing Verilog.

Validation performed:

• make MODULES="$PWD" import exited 0.
• make MODULES="$PWD" analysis exited 0, analyzing 491 files with no errors or warnings.
• Full cocotb regression passed with CI's own invocation, pytest -n auto --dist=worksteal tests: 911 passed, 21 skipped, no failures. The skips are pre-existing.
• VSG reported no violations.

Related

• Convert ethernet/RoCEv2 to pure VHDL, removing all generated Verilog and the 36 CRC table files #1468 removes the Verilog under ethernet/RoCEv2.