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Convert ethernet/RoCEv2 to pure VHDL, removing all generated Verilog and the 36 CRC table files - #1468

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Convert ethernet/RoCEv2 to pure VHDL, removing all generated Verilog and the 36 CRC table files#1468
ruck314 wants to merge 15 commits into
pre-releasefrom
roce-vhdl-refactor

docs(rocev2): record the conversion where a maintainer will look

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