open-source-eda

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

OpenRule1umPDKを各種環境にセットアップするためのスクリプトです。

Traceable datasheet-to-SPICE model generation for power MOSFETs and diodes, with browser extraction and validation benchmarks.

Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation

AI-assisted RFIC optimization framework combining ONNX surrogate models, Qucs-S/Xyce circuit simulation, and AWS Palace fine-tuning for open-source electronic design automation (EDA).

Open-source MBIST generator for OpenRAM SRAM macros with built-in BIRA/BISR redundancy repair, plus a programmable march-algorithm fault-model research platform

SHA-256 accelerator on Caravel SoC (SkyWater 130nm) - open-source RTL-to-GDSII signoff flow

A curated list of semiconductor industry resources, with a deliberate bias toward sub-10nm logic, lithography, process technology, and advanced packaging.

This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.

4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

Tiny Tapeout TTSKY26c (sky130A): on-chip metastability characterizer -- ring-osc async data + 41-tap delay line + dual-sample witness FFs; raw UART stream for tau/W and MTBF extraction

Landing page for AI agent tooling for hardware + ML systems (MCP, skills, EDA containers)

A decode-phase KV-cache engine for LLM inference: SystemVerilog RTL to a sign-off-clean GDSII on SkyWater 130nm (0 DRC, 0 LVS, timing closed), with a formally proved paged allocator and a 16-node sequence-parallel mesh over a torus NoC.

Research portfolio on analog layout techniques, structure-aware generation, B*-tree placement, well-domain repair, and access-aware routing.

Curso de UVM en español que corre entero con Verilator, sin licencias de EDA. 6 días, 24 capítulos, 274 slides y 32 ejemplos ejecutables con cobertura funcional, más ejercicios que se corrigen solos. Gratis, CC BY 4.0.

A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.

An open-source agent that designs and verifies digital hardware, recording every attempt as an open dataset of Verilog design and repair.

Block-RAM memory subsystem through the open-source iCE40 flow (Yosys, nextpnr, icetime, icepack) on two devices, with the same tests passing on RTL and on the mapped netlist.

Model Context Protocol server for Yosys RTL synthesis, cell statistics, and latch triage

Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.