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Md Zesun Ahmed Mia — AI Agent Tooling for Hardware + ML Systems

PhD candidate in Electrical Engineering at Penn State · Ex-Micron ML engineer intern · Ex-Intel graduate technical intern. I build MCP servers, agent skills, and CLIs that turn AI coding agents into capable hardware and ML-systems engineers.

License: Apache-2.0 CI Standard: Strict Platforms: Linux-first Made by zesun33 Landscape: 100+ tools

Identity

  • Name: Md Zesun Ahmed Mia
  • Role: PhD Candidate, Electrical Engineering, Penn State
  • Focus: Neuromorphic computing · Compute-in-Memory (CIM) · ML accelerators · Hardware-aware ML
  • Industry: Ex-Micron ML engineer intern (CIM-NVM pathfinding & LLM serving disaggregation) · Ex-Intel graduate technical intern (thin film process & AI process models)
  • Selected work: TrilinearCIM (arXiv 2604.07628) · RMAAT (ICLR 2026)
  • Website: zesun33.github.io

This repository is the landing page for a family of open-source hardware-agent tools. Shipped items clear the engineering gates below; planned items are sequenced in ROADMAP.md and are not installable yet.

One-step install (npm vs npx)
npm Node's package installer. Puts a package in node_modules or globally (npm i -g).
npx Runs a package once. No global install. npx pkg downloads (if needed) and executes.
One-step npx @zesun33/create-hw-agent my-asic writes a project whose .cursor/mcp.json starts every MCP server with npx -y (for example @zesun33/mcp-verilog). Then make images pulls ghcr.io/zesun33/{verilog,asic,fpga,spice}. 
npx @zesun33/create-hw-agent my-asic
cd my-asic && make images && make sim

Until the scoped packages are on the npm registry, clone zesun33/hw-agent-scaffold and run node bin/create-hw-agent.js ./my-asic. You can npm login (OAuth is fine) when you are ready to npm publish. Do not paste tokens into chat.

AI Agent Tools — the new family

These are agent-facing tools: MCP servers, agent skills, and CLIs that any modern coding agent or AI IDE (Cursor, Windsurf, GitHub Copilot / OpenAI Codex, Claude Code, Google Antigravity, OpenCode, Cline) can call via the open Model Context Protocol (MCP).

Repo Stack What it does Status
eda-docker-images Docker · Podman Shared Verilog / SPICE / FPGA / ASIC images on public GHCR (ghcr.io/zesun33/...). ✅ Shipped
eda-devcontainer Dev Containers VS Code / Cursor profiles on top of those images. ✅ Shipped
mcp-verilog TypeScript · MCP Lint, compile, simulate, VCD summaries, Verilator coverage, testbench generation. ✅ Shipped (v0.2.0)
hw-agent-skills Markdown · Skills 8 portable skills (rtl-reviewer, synthesis-triage, kernel-roofline, asic-flow-operator, formal-operator, signoff-operator, fpga-operator). ✅ Shipped
mcp-cocotb TypeScript · MCP Run cocotb testbenches, collect results, and surface failing assertions. ✅ Shipped
mcp-yosys TypeScript · MCP Synthesize RTL, return cell count, hierarchy, and warnings as structured JSON. ✅ Shipped
mcp-rtl-review TypeScript · MCP Static RTL review (width mismatches, missing resets, blocking vs non-blocking). ✅ Shipped
mcp-openroad TypeScript · MCP Floorplan, place, CTS, PDN, route, STA (Nangate45 + Sky130). ✅ Shipped (v0.2.3)
mcp-gds TypeScript · MCP GDSII stream-out, KLayout DRC smoke, Netgen LVS, Magic extraction. ✅ Shipped
mcp-formal TypeScript · MCP SymbiYosys BMC/prove (smtbmc+z3) with honest 5-state verdicts. ✅ Shipped
mcp-fpga TypeScript · MCP iCE40/ECP5 synth, nextpnr P&R, bitstream packing, iceprog/openFPGALoader. ✅ Shipped
mcp-spice TypeScript · MCP ngspice batch simulate + .meas JSON. ✅ Shipped
hw-agent-scaffold Node · npx One-step: npx @zesun33/create-hw-agent scaffolds RTL + all MCP servers. ✅ Shipped
kernel-forge Python CLI · CUDA Developer CLI, microbenchmarking, and Roofline model analysis for GPU kernels. ✅ Shipped
agentic-asic Python CLI · MCP Client Autonomous silicon compilation: RTL → review → simulate → formal → synth → P&R → GDS/LVS signoff, plus an FPGA track. Sky130 scale vehicle LVS-matched. ✅ Shipped (v0.2.1)
gh-actions-for-hw GitHub Actions Reusable hardware CI composites on GHCR EDA images (lint, sim, cocotb, yosys, OpenROAD, ngspice). ✅ Shipped

Legend: 🚧 Building · 📋 Planned · ✅ Shipped · ⛔ Blocked

⚡ Quick Tour: The Autonomous Hardware Agent in Action

How the entire stack works together in closed-loop design:

┌─────────────────────────────────────────────────────────────────────────────┐
│ 1. COGNITIVE LAYER (hw-agent-skills)                                        │
│    Agent checks rtl-reviewer & verilog-testbench-writer rubrics.            │
│    Enforces: non-blocking '<=', latch prevention, $fatal assertion suites.  │
└──────────────────────────────────────┬──────────────────────────────────────┘
                                       │ generates clean RTL & testbench
                                       ▼
┌─────────────────────────────────────────────────────────────────────────────┐
│ 2. PROTOCOL BRIDGE (mcp-verilog)                                            │
│    Agent calls verilog_simulate or verilog_lint over stdio JSON-RPC.        │
│    Replaces 5,000 lines of noisy terminal output with `< 100 tokens` of JSON. │
└──────────────────────────────────────┬──────────────────────────────────────┘
                                       │ dispatches command with timeout guard
                                       ▼
┌─────────────────────────────────────────────────────────────────────────────┐
│ 3. ISOLATED RUNTIME (eda-docker-images & eda-devcontainer)                  │
│    Executes iverilog 12.0 / Verilator 5.050 inside rootless Podman.         │
│    Zero host install, zero sudo, single-user namespace compatible.          │
└─────────────────────────────────────────────────────────────────────────────┘

The 3-Step Closed-Loop Execution

1. Static Audit via hw-agent-skills

Before compiling, the agent applies the rtl-reviewer skill to detect common synthesis hazards:

✔ Checked: All sequential assignments use non-blocking '<='
✔ Checked: All combinational branches cover default values (no inferred latches)
✔ Checked: Active-low asynchronous reset (rst_n) cleanly decoupled from clock

2. Dispatched via mcp-verilog (< 100 Tokens)

The agent calls verilog_simulate to execute the design against its self-checking testbench:

{
  "method": "tools/call",
  "params": {
    "name": "verilog_simulate",
    "arguments": {
      "files": ["counter.v", "counter_tb.v"],
      "top_module": "counter_tb"
    }
  }
}

3. Bounded Simulation inside eda-docker-images (318ms)

The server mounts the workspace into the eda-docker-images Verilog container and returns structured results:

{
  "success": true,
  "exitCode": 0,
  "timedOut": false,
  "stdout": "PASS: Counter testbench completed successfully with count=5\n",
  "errors": []
}

See LANDSCAPE.md for the full competitive analysis: 100+ tools surveyed across 14 domains — RTL, FPGA, synthesis, P&R, verification, SPICE, TCAD, device physics, neuromorphic/SNN, analog AI, architecture simulation, emerging devices (FeFET/MRAM/memristor), PCB, and quantum hardware.

Optional, deferred: astromorph and trilinearcim (paper-linked research code) are intentionally not in this wave. They can be added later if there is a need for paper-aligned open-source software.

Hardware + ML Systems

Code that demonstrates the underlying competence the agent tools sit on.

Area Evidence
ML accelerators / CIM TrilinearCIM (DG-FeFET, 3-operand MAC, runtime-reprogram-free attention).
Efficient attention RMAAT — astrocyte-inspired long-context transformer (ICLR 2026).
Hardware-aware ML Mixed-precision, quantization, sparsity, kernel co-design experience.
ASIC / RTL Verilog, SystemVerilog, synthesis, P&R, DFT, static timing (cadence + academic tools).
EDA Cadence Virtuoso, HSPICE, TCAD Sentaurus, yosys, OpenROAD, Verilator, cocotb.
Programming Python, CUDA, C/C++, Triton, PyTorch, TensorRT, ONNX, MATLAB, Verilog.

Existing Systems Work

Earlier self-study repos demonstrating systems-level fluency. Kept as supporting evidence, not the main act.

Repo Topic
cuda-gemm-optimization Naive → tiled → Tensor Core GEMM.
cuda-memory-benchmark Global/shared memory bandwidth, roofline, bank conflicts.
parallel-computing-lab OpenMP patterns and a parallel GEMM.
resnet-tensorrt-bench FP32 / FP16 / INT8 inference through TensorRT.
triton-flash-attention-lite FlashAttention in Triton, block-level memory management.

Research

Venue Paper Year
ICLR RMAAT: Astrocyte-Inspired Memory Compression and Replay for Efficient Long-Context Transformers 2026
arXiv Trilinear Compute-in-Memory Architecture for Energy-Efficient Transformer Acceleration 2026
IEEE TCDS Delving deeper into astromorphic transformers 2025
ICONS Neuromorphic Cybersecurity with Semi-Supervised Lifelong Learning 2025
MWSCAS Toward Variation-Tolerant Ferroelectric Neural Computing 2025
Matter (Cell) Self-sensitizable neuromorphic device based on adaptive hydrogen gradient 2024

Google Scholar: j-zfUj8AAAAJ

Skill Matrix

Skill Strongest evidence today
DevOps / EDA containers eda-docker-images, eda-devcontainer
Existing systems depth cuda-gemm-optimization, cuda-memory-benchmark, parallel-computing-lab
ML systems awareness triton-flash-attention-lite, research (CIM / RMAAT)
Research depth ICLR 2026, IEEE TCDS, Matter (Cell Press)
MCP / agent tooling (shipped) mcp-verilog, hw-agent-skills, agentic-asic, nine EDA MCP servers, npx @zesun33/create-hw-agent

Verified On

CI for this landing page runs on ubuntu-latest. Container tools are verified on Linux hosts (Docker/Podman). macOS/Windows can pull the same public GHCR images — not claimed as CI-verified yet.

Repo Linux macOS Windows Agents verified
hw-agent-tooling ✅ (CI) — — n/a
eda-docker-images ✅ (local smokes) —¹ —¹ n/a
eda-devcontainer ✅ (local smokes) —¹ —¹ n/a
mcp-verilog ✅ (CI) 📋 📋 ✅
hw-agent-skills ✅ (CI) 📋 📋 ✅
mcp-cocotb ✅ (CI) 📋 📋 ✅
mcp-yosys ✅ (CI) 📋 📋 ✅
mcp-rtl-review ✅ (CI) 📋 📋 ✅
mcp-openroad ✅ (CI) ⛔ ⛔ ✅
mcp-gds ✅ (CI) ⛔ ⛔ ✅
mcp-formal ✅ (CI) 📋 📋 ✅
mcp-fpga ✅ (CI) 📋 📋 ✅
mcp-spice ✅ (CI) 📋 📋 ✅
hw-agent-scaffold ✅ (CI) 📋 📋 n/a
kernel-forge ✅ (CI) 📋 📋 ✅
agentic-asic ✅ (CI) ⛔ ⛔ ✅
gh-actions-for-hw ✅ (CI) 📋 📋 n/a

¹ Container images may run on macOS/Windows hosts; not part of current CI.

"Agents verified" = installed and exercised in Claude Code, OpenCode, OpenAI Codex, and Cursor with one happy-path and one failure-path transcript recorded in the repo.

How to use this portfolio

  • Recruiters / hiring managers: Start with the Skill Matrix; the end-to-end demo lives in agentic-asic (asic demo, Sky130 regfile32x32).
  • Hardware engineers: Use eda-docker-images / eda-devcontainer today; pull ghcr.io/zesun33/{verilog,asic,fpga,spice}.
  • Agent builders: npx @zesun33/create-hw-agent plus hw-agent-skills is the install path.
  • Researchers: See the Research section for the papers behind the design choices.

Engineering Standard

Every repo in this family ships behind the same gates. No repo goes public without clearing all of them. See CONTRIBUTING.md and the per-repo ## Verification sections.

Gate What it catches
Spec lock Scope creep, ambiguous contracts
Static quality Formatter, linter, type errors
Unit tests Logic regressions
Fixture integration Real-world toolchain mismatches
Packaging / install "Works on my machine" failures
Protocol / contract MCP JSON-RPC drift, schema breakage
Docs verification Stale quickstarts, broken links
Agent integration matrix Client-specific breakage
Release candidate Last-mile regressions
Post-publish smoke Tag-vs-source drift

Contact

License

Apache-2.0. © 2026 Md Zesun Ahmed Mia.

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Landing page for AI agent tooling for hardware + ML systems (MCP, skills, EDA containers)

zesun33.github.io

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agent-toolingai-codingcudaedahardware-engineeringmcpopen-source-edapersonal-projectsverilog

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