Master's student in Computer Science with a Bachelor's in Electronics and Communication Engineering specializing in ASIC and VLSI. Skilled in Verilog/System Verilog, Synopsys and Cadence design flows, and digital design methodologies from RTL to gate-level implementation. Experienced in RTL coding, synthesis, timing analysis, and debugging with strong problem-solving skills. Passionate about building reliable and high-performance integrated circuits for next-generation technologies.

mindmap
  root((ASIC/VLSI<br/>Expertise))
    Design
      RTL Coding
      Verilog
      SystemVerilog
      Synthesis
      Timing Analysis
    Verification
      UVM
      DDR5 Verification
      Testbench Development
      Regression Debugging
    Physical Design
      Layout Generation
      DRC/LVS
      PEX
      GDSII
    Tools
      Synopsys VCS
      Verdi
      Magic VLSI
      Xschem
      ngspice
      KLayout

timeline
    title Career Timeline
    section 2019-2021
        Jul 2019 : Testing Engineer
                 : Sasmos HET Technologies
                 : Defense & Aerospace Projects
    section 2021-2022
        May 2021 : Catalog Associate
                 : Amazon
                 : Graphics SOC Integration
    section 2022-2023
        2022 : Design & Verification Engineer
             : Tech Mahindra Cerium
             : Client Intel
             : DDR5 Memory Controller
    section 2026-Present
        Apr 2026 : VLSI Design Intern
                 : Quantum GenInc
                 : CMOS IC Design Flow
                 : 130nm Technology

Quantum GenInc - VLSI Design Intern (Apr 2026 – Present)

Participating in an industry-oriented VLSI design internship focused on the complete CMOS IC design flow, progressing from schematic capture to GDSII generation using a 130nm Process Design Kit (PDK).

Key Responsibilities:

• Designing transistor-level CMOS inverter schematics using Xschem and validating functionality through ngspice DC and transient simulations
• Performing circuit characterization by analyzing Voltage Transfer Characteristics (VTC), propagation delay, rise/fall time, switching threshold, and fan-out effects
• Optimizing PMOS/NMOS transistor sizing to study driving strength, noise margins, and power-delay trade-offs
• Learning physical design methodologies including layout generation, Design Rule Check (DRC), Layout Versus Schematic (LVS), parasitic extraction (PEX), post-layout simulation, and GDSII generation
• Working in a Linux-based environment using open-source EDA tools including Xschem, ngspice, Magic VLSI, and KLayout while following industry-standard IC design and verification workflows

• Layout Generation & Optimization
• Design Rule Check (DRC)
• Layout Versus Schematic (LVS)
• Parasitic Extraction (PEX)
• Post-layout Simulation
• GDSII Generation

Parameterized AXI4-Lite crossbar with a layered UVM-style verification environment

A configurable AXI4-Lite crossbar (default 2 masters × 3 slaves, re-elaborated as 3×4) built around a two-pass round-robin arbiter, base/mask address decode, and an internal DECERR responder for unmapped addresses. Because AXI4-Lite carries no transaction IDs, per-master order queues and per-slave owner queues enforce in-order responses; deadlock freedom follows from a global arrival-time ordering argument documented in the repo.

Key Features:

• 10/10 tests passing on both 2×3 and 3×4 elaborations
• 100% functional coverage — 42/42 bins (2×3), 52/52 bins (3×4)
• 2,040 scoreboard checks across the regression
• Injected routing bug caught by 7/10 tests: 420 routing, 179 response, 73 data errors

Technologies: SystemVerilog UVM Cocotb Verilog AXI4-Lite Verification Coverage

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APB3 CSR block with full register abstraction layer

APB3-mapped CSR block covering RW/RO/W1C/RC/RAZ-WI with a full register abstraction layer: front-door and back-door access, reset checks on both, and a mirror that catches a back-door poke.

Key Features:

• 8 registers with comprehensive access policies
• Front-door and back-door verification
• Symbolic-value integrity proofs
• 369 field comparisons, 0 mismatches

Technologies: SystemVerilog Python UVM Verification APB CSR RAL Cocotb

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DDR3-style memory controller with assertion-based timing checking

DDR3-style memory controller (8 banks, bank-parallel scheduler, auto-refresh) with assertion-based timing checking: 0 violations across 12 JEDEC parameters, each with a measured margin.

Verification Results:

• 12 JEDEC timing parameters verified
• 261 read-data comparisons against golden memory
• 427 writes successfully applied
• 100% functional coverage (83/83 bins)
• 0 timing violations across all tests

Technologies: SystemVerilog Cocotb DDR3 DRAM SVA Assertions Verilator

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Gray-pointer async FIFO with metastability model

Gray-pointer asynchronous FIFO with two-flop synchronizers, verified against unrelated clocks and a behavioral metastability model that the binary-pointer version fails.

CDC Verification:

• 513 sampled values, all drawn from real source values
• 511 pointer transitions, max bits changed = 1
• 609 words verified across 11 scenarios
• 5 clock ratios tested (0.13× to 7.67×)

Technologies: Verilog Cocotb CDC Clock Domain Crossing Gray Code Metastability

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Formal proof of arbiter, FIFO, and AXI4-Lite slave

Formal proof with SymbiYosys: 25 assertions proved unbounded, 13/13 covers reached, and a broken arbiter that passes every safety property.

Formal Results:

• 11/11 formal tasks gave required results
• 25 assertions + 13 cover statements
• All proofs unbounded (k-induction ×2, PDR/IC3 ×1)
• 100% non-vacuity verification

Technologies: SystemVerilog SVA Formal Verification SymbiYosys Yosys K-Induction

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Configurable SPI VIP proven across 2 DUTs

A reusable SPI Verification IP with documented API - driver, monitor, protocol checker, scoreboard, coverage - proven reusable across two unrelated DUTs and seven configurations by source fingerprint.

VIP Features:

• 7 configurations exercised
• 2 structurally unrelated DUTs
• 100% coverage (33/33 bins)
• 9 protocol rules validated
• SHA-256 fingerprint proves zero modification

Technologies: Python SystemVerilog Cocotb UVM SPI Protocol Verification IP

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Block-RAM subsystem through open-source iCE40 flow

Block-RAM memory subsystem through the open-source iCE40 flow (Yosys, nextpnr, icetime, icepack) on two devices, with the same tests passing on RTL and on the mapped netlist.

Implementation Results:

• Fmax 129.58 MHz (HX8K) vs 12 MHz target (10.8× margin)
• Fmax 45.74 MHz (UP5K) (3.8× margin)
• 8 × SB_RAM40_4K block RAMs inferred
• 486/7680 LC (6.3%) utilization
• 7/7 tests PASS on both RTL and gate-level netlist

Technologies: Verilog FPGA Yosys nextpnr iCE40 Synthesis Place-and-Route

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32×8 SRAM with MBIST running MATS+ and March C-

32×8 SRAM with an MBIST controller running MATS+ and March C- against six runtime-injected fault models - including a coupling fault that MATS+ misses and March C- catches.

MBIST Results:

• 6 fault models injected at runtime
• MATS+ 545 cycles, March C- 1121 cycles
• Ratio 2.06 matches 5N vs 10N complexity
• Coupling fault: MATS+ MISSED, March C- DETECTED
• 100% coverage (15/15 bins)

Technologies: SystemVerilog Cocotb MBIST DFT March Test Fault Injection

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INV/NAND2/NOR2/DFF characterized on sky130 into Liberty timing models

Characterization of a small cell library — INV, NAND2, NOR2 and a positive-edge DFF — into a Liberty (.lib) file per PVT corner that a synthesis or STA tool can read directly. Delay and transition are swept across four input slews and four output loads at three corners, varying process and voltage and temperature together.

Key Features:

• 288 measured SPICE points, 21/21 validation checks passing
• 3 .lib files, 24 NLDM tables each, all 4×4 and brace-balanced
• DFF setup 12.5 / 15.0 / 25.0 ps and hold −12.5 / −10.0 / 0.0 ps across ff/tt/ss
• Inverter noise margins positive at all corners; butterfly SNM 0.593 – 0.753 V

Technologies: Python ngspice sky130 Liberty NLDM STA Characterization

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Schematic → simulation → layout → DRC → LVS on the SkyWater 130 nm PDK

A complete full-custom flow for a CMOS inverter on sky130A, taken from schematic through SPICE characterization to a GDS layout signed off against the PDK's own sky130A_mr.drc and sky130.lvs rule decks — not a hand-written subset — so "DRC clean" and "LVS match" mean what they mean in industry.

Key Features:

• DRC: 0 violations against the official sky130A deck
• LVS: "Congratulations! Netlists match." — 2/2 devices, 4/4 nets, 4/4 pins
• 5 PVT corners, switching threshold VM 0.699 – 1.028 V, noise margins positive throughout
• Negative controls prove the checks work: DRC flags an illegal layout, LVS flags a shorted output

Technologies: sky130 ngspice KLayout DRC LVS Python Physical Design

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