design-verification-project

Here are 5 public repositories matching this topic...

abdo-ehab-euv / sram-controller-uvm-verification

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project

Updated May 14, 2026
SystemVerilog

umeshchess / sync-fifo-verilog

Star

Synchronous FIFO

linux fedora verilog fifo vlsi verilog-project vlsi-design design-verification verilog-code vlsi-project fedora-linux design-verification-project synchronous-fifo

Updated Aug 10, 2026
Verilog

sriram-dv / axi4-lite-uvm

Star

this is my final year project.

system-verilog axi4-lite uvm-verification design-verification-project

Updated Apr 30, 2026
SystemVerilog

raviranjan-vlsi / AMBA-AHB-Memory-Verification

Star

AMBA AHB-Lite Memory Verification using SystemVerilog — constrained-random verification, functional coverage, SVA assertions, scoreboard, monitor, driver, and all 8 AHB burst types.

assertions systemverilog code-coverage vlsi questasim testbench amba sva ahb3lite-memory ahb ahb-lite design-verification constrained-random-verification functional-coverage amba-project questa-sim design-verification-project amba-ahb

Updated Aug 17, 2026
SystemVerilog

Karan-nevage / D-Flip-Flop-Design-Verification-Using-UVM

Star

This project demonstrates design verification of a D Flip Flop using UVM methodology. It includes driver, monitor, scoreboard, and testbench components to validate functionality, ensure correct timing, and report mismatches. A clean, modular flow highlights reusable verification practices.

systemverilog uvm design-verification uvm-verification d-flip-flop d-flipflop-uvm-verification design-verification-project

Updated Jan 7, 2026
SystemVerilog

Add this topic to your repo

To associate your repository with the design-verification-project topic, visit your repo's landing page and select "manage topics."

Learn more