AMBA AHB Protocol implementation in Verilog with Single Master and Four Slaves including Decoder, Multiplexer, FSM based Master, Memory Mapped Slaves and Testbench Verification.
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Updated
Jun 5, 2026 - Verilog
AMBA AHB Protocol implementation in Verilog with Single Master and Four Slaves including Decoder, Multiplexer, FSM based Master, Memory Mapped Slaves and Testbench Verification.
Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.
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