amba-project

Here are 4 public repositories matching this topic...

JAYRAM711 / AHB2APB-PROTOCOL-BRIDGE

The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB

verilog-hdl amba-project ahb-apb bridge-interfacing

Updated May 6, 2026
Verilog

ArtesGC / NGuimbi-Crawler

Star

server and web browser

crawler browser pyqt5-desktop-application python-browser awesome-made-by-angolans qss-design amba-project

Updated Jul 30, 2021
Python

raviranjan-vlsi / AMBA-AHB-Memory-Verification

Star

AMBA AHB-Lite Memory Verification using SystemVerilog — constrained-random verification, functional coverage, SVA assertions, scoreboard, monitor, driver, and all 8 AHB burst types.

assertions systemverilog code-coverage vlsi questasim testbench amba sva ahb3lite-memory ahb ahb-lite design-verification constrained-random-verification functional-coverage amba-project questa-sim design-verification-project amba-ahb

Updated Aug 17, 2026
SystemVerilog

raviranjan-vlsi / AMBA-AHB-Master-Slave-Interface-

Star

Verilog implementation of AMBA AHB Master and Slave with FSM control, FIFO integration, burst transfer (INCR4), and waveform-based protocol verification.

rtl verilog vivado soc vlsi digital-design ahb verilog-project vlsi-project rtl-design bus-protocol amba-project rtl-verification amba-ahb ahb-master ahb-slave

Updated May 8, 2026
Verilog

Add this topic to your repo

To associate your repository with the amba-project topic, visit your repo's landing page and select "manage topics."

Learn more