delay-propogation

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hlibstrochkovskyi / dbsim

Headless, event-driven simulation of the German railway (Deutsche Bahn) network — a research tool for studying delay propagation, capacity bottlenecks, and dispatching strategies across macroscopic, mesoscopic, and microscopic scales.

python simulation optimization railway deutsche-bahn operations-research discrete-event-simulation delay-propogation

Updated Jun 15, 2026
Python

anthony7586 / designing-with-VHDL

Star

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

fsm delay vhdl finite-state-machine battleship fulladder battleship-game seven-segments-display flip-flop flip-flops ripple-carry-adder adder-subtractor next-state-logic delay-propogation

Updated Dec 28, 2023

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