GitHub - anthony7586/designing-with-VHDL: porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

Name		Name	Last commit message	Last commit date
Battleship.zip		Battleship.zip
D_Flip_Flop.zip		D_Flip_Flop.zip
Delay_Propogation.zip		Delay_Propogation.zip
FSM.zip		FSM.zip
Fulladder.zip		Fulladder.zip
NSL.zip		NSL.zip
RCA.zip		RCA.zip
SSDD.zip		SSDD.zip
counter.zip		counter.zip

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porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation

adder-subtractor battleship battleship-game delay delay-propogation finite-state-machine flip-flop flip-flops fsm fulladder next-state-logic ripple-carry-adder seven-segments-display vhdl

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