cadence-spectre

Python interface for Cadence Spectre

Read .raw simulation files as pandas DataFrame

Python SDK to run simulation on cadence and automate process.

Library of Verilog-A models

A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)

MATLAB toolbox to read HSPICE generated output files

PTM models for spectre and ACE

Its a project which contains the DC analysis of a 6T SRAM and more

Collection of functions to test standard cells

VLSI Design Project as part of Purdue's ECE559 Coursework

Full Adder using transmission gate logic circuit Layout

8-bit 5 MHz Split-CDAC Asynchronous SAR ADC with SkyWater SKY130 nm PDK, Cadence Virtuoso/Spectr

Thesis companion workflow for AI-assisted modeling, Spectre/OCEAN automation, and model-independent validation examples.

Shunt-Feedback and Regulated-Cascode TIA design and simulation in SkyWater SKY130 130nm CMOS

Haskell module for interacting with Cadence Spectre

Configure 6T SRAM memory to switch between SRAM, BCAM, and TCAM mode, allowing to perform search logic

Designed and implemented a performance-balanced noise-canceling LNA in SCL 180nm CMOS using Cadence Virtuoso, covering CG-CS, Cascode, and Folded-Cascode architectures, RF analysis, full-custom layout, DRC/LVS, PEX, and a custom spiral inductor.

Every chip needs ESD protection or it doesn't survive its first handshake with reality. Here's one — designed, simulated, and debugged from scratch in Cadence Virtuoso, including a real PDK toolchain bug found and fixed along the way.