🚀 FSM-Based Parameterized UART Transceiver (Verilog RTL)

A synthesizable UART communication controller featuring FSM-based transmitter, receiver, parameterized baud-rate generation, and end-to-end loopback verification.

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📌 About This Project

This repository implements a Universal Asynchronous Receiver Transmitter (UART) in Verilog RTL, designed using independent Finite State Machines (FSMs) for both transmission and reception.

The design supports configurable baud rates through parameterization, converts parallel data to serial format for transmission, reconstructs serial data back into parallel format at the receiver, and validates complete end-to-end communication using self-checking Verilog testbenches.

The project follows a modular RTL design methodology commonly used in FPGA and ASIC development.

💡 Developed, simulated, and verified using Icarus Verilog and GTKWave.

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✨ Features

• ✅ FSM-Based UART Transmitter
• ✅ FSM-Based UART Receiver
• ✅ Parameterized Baud Rate Generator
• ✅ Parallel-to-Serial Data Conversion
• ✅ Serial-to-Parallel Data Conversion
• ✅ Start Bit Detection
• ✅ Stop Bit Verification
• ✅ Busy Status Signal
• ✅ Loopback Communication Verification
• ✅ Synthesizable RTL Design
• ✅ Self-Checking Testbench
• ✅ GTKWave Timing Verification

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🏗️ Project Architecture

                 +----------------------+
                 |      UART TX         |
                 |  FSM-Based Encoder   |
                 +----------+-----------+
                            |
                            | TX
                            |
                    Serial Communication
                            |
                            |
                 +----------v-----------+
                 |      UART RX         |
                 |  FSM-Based Decoder   |
                 +----------+-----------+
                            |
                     Parallel Data Out

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📂 Repository Structure

FSM-Based-Parameterized-UART-Transceiver-Verilog-RTL/
│
├── RTL/
│   ├── uart_tx.v
│   ├── uart_rx.v
│   └── uart_top.v
│
├── TB/
│   ├── uart_tx_tb.v
│   └── uart_system_tb.v
│
├── images/
│   └── uart_waveform.png
│
├── .gitignore
├── LICENSE
└── README.md

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⚙️ Design Modules

Module	Description
uart_tx.v	UART Transmitter implemented using an FSM
uart_rx.v	UART Receiver implemented using an FSM
uart_top.v	Integrates transmitter and receiver into a loopback system
uart_tx_tb.v	Testbench for standalone transmitter verification
uart_system_tb.v	End-to-end loopback verification testbench

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🔄 UART Transmission Flow

Idle
   │
   ▼
Start Bit
   │
   ▼
Transmit 8 Data Bits
   │
   ▼
Stop Bit
   │
   ▼
Return to Idle

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📡 Receiver Operation

The UART receiver continuously monitors the serial input line.

1. Detects the Start Bit
2. Samples each incoming data bit according to the configured baud timing
3. Reconstructs the original 8-bit data
4. Verifies the Stop Bit
5. Asserts data_valid once a complete frame has been received successfully

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🛠️ Tools Used

Tool	Purpose
Verilog HDL	RTL Design
Icarus Verilog	Simulation
GTKWave	Waveform Analysis
VS Code	Development Environment
Git	Version Control
GitHub	Repository Hosting

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▶️ Running the Project

Compile

iverilog -g2012 -o uart_system_sim RTL/uart_tx.v RTL/uart_rx.v RTL/uart_top.v TB/uart_system_tb.v

Run Simulation

vvp uart_system_sim

Open Waveform

gtkwave simulation/uart_system.vcd

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📈 Simulation Result

After simulation, the following functionality is verified:

• UART transmission begins after tx_start
• Start bit generation
• Sequential transmission of all data bits
• Stop bit generation
• Receiver reconstructs transmitted byte
• data_valid asserted after successful reception
• End-to-end loopback communication verified

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🎯 Skills Demonstrated

This project demonstrates practical knowledge of:

• Finite State Machine (FSM) Design
• RTL Design Methodology
• Verilog HDL
• UART Communication Protocol
• Digital Communication Systems
• Parameterized Hardware Design
• Modular RTL Architecture
• Testbench Development
• Functional Verification
• Timing-Based Digital Design
• Waveform Debugging
• FPGA/ASIC Design Fundamentals

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🚀 Future Improvements

• Configurable data width
• Configurable parity generation/checking
• Even/Odd parity support
• Multiple stop-bit configuration
• FIFO buffering
• Interrupt generation
• APB/AHB interface
• FPGA implementation on development board

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📜 License

This project is licensed under the MIT License.

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👨‍💻 Author

Abhishek Mohammad

B.Tech in Electronics & Communication Engineering
National Institute of Technology (NIT) Jalandhar

Areas of Interest

• RTL Design
• Digital System Design
• Embedded Systems
• FPGA & ASIC Design
• RISC-V Processor Design
• VLSI Design & Verification

GitHub:
https://github.com/abhishekxece

LinkedIn:
https://www.linkedin.com/in/abhishek-mohammad-377071325/

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⭐ If you found this project useful, consider giving it a star. Feedback and contributions are always welcome!