Configurable APB4 Peripheral using SystemVerilog

Overview

A configurable APB4-compliant peripheral designed and verified using SystemVerilog.

The project implements an APB4 slave interface with configurable control, status, configuration, data, interrupt, version, and scratch registers. It also includes functional verification, APB protocol assertions, and RTL synthesis using Yosys.

Features

• APB4 slave interface
• 32-bit address and data width
• Zero-wait-state APB transfers
• Configurable control and configuration registers
• DATA register
• STATUS register with BUSY, DONE, ERROR, and IRQ status
• START → BUSY → DONE operation
• Interrupt enable and status registers
• Write-one-to-clear interrupt status
• Fixed VERSION register
• Scratch register for software testing
• Invalid-address detection using PSLVERR
• SystemVerilog testbench
• APB protocol assertions
• VCD waveform generation
• RTL synthesis and technology mapping using Yosys

Register Map

Address	Register	Access	Description
0x00	CONTROL	R/W	Enable and START control
0x04	STATUS	R	BUSY, DONE, ERROR, IRQ
0x08	CONFIG	R/W	Peripheral configuration
0x0C	DATA	R/W	Data register
0x10	IRQ_ENABLE	R/W	Interrupt enable
0x14	IRQ_STATUS	R/W	Interrupt status / clear
0x18	VERSION	R	Version = 0x00010000
0x1C	SCRATCH	R/W	Software test register

CONTROL Register

Bit	Name	Description
0	ENABLE	Peripheral enable
1	START	Starts an operation
2	SOFT_RESET	Reserved/control field

STATUS Register

Bit	Name	Description
0	BUSY	Operation in progress
1	DONE	Operation completed
2	ERROR	Invalid access/write error
3	IRQ	Interrupt output status

Verification

The design was verified using a SystemVerilog testbench and APB protocol assertions.

Verification includes:

• Reset-value checks
• CONTROL register read/write
• CONFIG register read/write
• DATA register read/write
• SCRATCH register read/write
• VERSION register verification
• STATUS verification
• START/BUSY/DONE behavior
• IRQ enable and IRQ status
• IRQ status clearing
• Invalid APB read
• Invalid APB write
• APB protocol assertions

Verification Result

16/16 checks passed

PASS COUNT = 16
FAIL COUNT = 0

*** ALL TESTS PASSED ***
Synthesis

RTL synthesis was performed using Yosys.

Synthesis Summary
Tool: Yosys 0.33
Top module: apb4_peripheral
RTL synthesis checks: 0 problems
Initial synthesized design: 62 cells
Technology-mapped netlist: results/apb4_peripheral_netlist.v
Technology-mapped design: 833 cells

The technology-mapped netlist contains basic logic cells including:

AND gates
OR gates
NOT gates
Multiplexers
D flip-flops with enable/reset
Project Flow
SystemVerilog RTL
       ↓
APB4 Register Design
       ↓
SystemVerilog Testbench
       ↓
Functional Verification
       ↓
APB Protocol Assertions
       ↓
Icarus Verilog Simulation
       ↓
VCD Waveform
       ↓
Yosys RTL Synthesis
       ↓
Technology Mapping
       ↓
Synthesized Netlist


Tools Used
SystemVerilog
Icarus Verilog
Yosys
Linux / WSL
Git
GitHub