Aspiring VLSI & ASIC Design Engineer
Building hands-on semiconductor & digital design projects
- Chennai, India
- in/kavinsrib
Popular repositories Loading
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dns-simulator
dns-simulator PublicPython-based simulation of recursive and iterative DNS resolution with TTL-based caching and latency modelling.
Python
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dma-controller-asic
dma-controller-asic PublicSystemVerilog DMA controller with RTL verification and ASIC synthesis flow using open-source VLSI tools.
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apb4-peripheral
apb4-peripheral PublicConfigurable APB4 peripheral designed and verified using SystemVerilog, with functional verification, protocol assertions, and Yosys synthesis.
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