Current-Starved Ring Oscillator PUF in 90nm CMOS — analog design in Cadence Virtuoso with behavioral verification in Vivado. Samsung Chip Design Studio project.
A Physical Unclonable Function (PUF) implemented using Current-Starved Ring Oscillators (CSRO) in 90nm CMOS. Designed in Cadence Virtuoso with behavioral verification in Vivado. Presented at Samsung Chip Design Studio, IIIT Bangalore.
| Phase | Status |
|---|---|
| Inverter characterization (Normal vs CS) | ✅ Complete |
| Deep-starved NMOS temperature sweep | ✅ Complete |
| 5-stage CSRO schematic + simulation | ✅ Complete |
| Behavioral Verilog model + testbench | ✅ Complete |
A Physical Unclonable Function generates a unique digital fingerprint from silicon manufacturing variation — no two chips respond identically to the same challenge input. Used in hardware security, device authentication, and key generation without non-volatile memory.
| Block | Description |
|---|---|
| Current-Starved Inverter | Bias-controlled delay cell — tuneable via Vbp/Vbn |
| 5-stage CSRO | Odd-stage ring oscillator — frequency set by bias |
| Arbiter | Captures frequency difference between two RO paths |
| Challenge Input | Selects RO pair for comparison |
| Test | Result |
|---|---|
| NMOS drain current @ 27°C | 92.3968 pA |
| NMOS drain current @ 125°C | 650.854 pA |
| CSRO oscillation | Verified — clean periodic output |
| Normal vs CS inverter | CSRO confirms bias-controlled delay advantage |
Verilog model simulates 2% frequency mismatch between RO pairs — backing the physical basis of the design.
| Challenge | PUF Response |
|---|---|
| 00 | 1 |
| 01 | 0 |
| 10 | 1 |
| 11 | 0 |
- Cadence Virtuoso (Schematic + Spectre simulation)
- Xilinx Vivado (Behavioral RTL verification)
- 90nm GPDK Process Node
| File | Description |
|---|---|
csro_stage.v |
Verilog behavioral model of CSRO stage |
puf_tb.v |
Challenge-response testbench |
Huang et al., TCAD 2024 | Srivastava et al., 2023