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1. UART-Echo-Verification UART-Echo-Verification Public

   UART transceiver with echo loopback — built from scratch in SystemVerilog and verified in Vivado simulation.

   Verilog 1

2. CSRO-PUF-90nm CSRO-PUF-90nm Public

   Current-Starved Ring Oscillator PUF in 90nm CMOS — analog design in Cadence Virtuoso with behavioral verification in Vivado. Samsung Chip Design Studio project.

   Verilog

3. RTL-to-GDS-II-90nm-Innovus RTL-to-GDS-II-90nm-Innovus Public

   Full Physical Design flow on a synchronous memory block — Cadence Innovus 21.15, 90nm process. Floorplan to GDSII with timing closure and physical verification.