A collection of hands-on FPGA development projects completed during summer 2026 using a modified LabVIEW environment capable of targeting generic FPGA devices, including an AMD/Xilinx Artix-7 FPGA.
The projects explore FPGA-based digital systems from both the hardware implementation and host-PC application perspectives. Rather than limiting LabVIEW to conventional NI hardware, this workflow was used to develop, integrate, simulate, and deploy FPGA logic for a non-NI FPGA platform.
These projects provided practical experience with:
- FPGA development using a modified LabVIEW FPGA toolchain
- Targeting an Artix-7 FPGA
- Hardware/FPGA communication interfaces
- UART/serial communication
- Gigabit Ethernet communication
- DDR3 memory read/write operations
- VHDL integration within the LabVIEW FPGA workflow
- EDF-based FPGA implementation flows
- FPGA simulation and generated simulation models
- FPGA bitstream generation and deployment
- Host-PC to FPGA communication
- PCIe/DMA-based data transfer concepts
The repository contains both the LabVIEW source projects and supporting FPGA/VHDL/EDF files used by the different experiments.
A major part of this training was learning how a graphical dataflow development environment can be used to describe and deploy hardware logic onto an FPGA outside of the normal NI FPGA ecosystem.
The modified LabVIEW environment provided an alternative hardware-development workflow in which LabVIEW diagrams could ultimately be mapped onto a generic FPGA target. This required working with the boundary between:
LabVIEW design → FPGA implementation → hardware interfaces → host-PC software
This made the training particularly useful for understanding FPGA systems beyond simply writing VIs for a PC.
This experiment develops UART communication using several implementation approaches.
The project contains LabVIEW FPGA VIs as well as supporting VHDL and EDF implementation/simulation files. The experiment includes separate versions for LabVIEW-based implementation, VHDL-based implementation, EDF-based implementation, and array-oriented data handling.
Key topics:
- UART transmit/receive logic
- FPGA serial communication
- LabVIEW FPGA implementation
- VHDL-based implementation
- EDF-based implementation
- Simulation support files
- Hardware/PC communication
This project was especially useful for comparing different ways of expressing essentially the same hardware functionality within an FPGA development flow.
This project explores FPGA-based Gigabit Ethernet communication, extending the work from low-speed serial communication toward higher-throughput networking.
The experiment focuses on the FPGA as a hardware communication endpoint and provides experience with implementing communication-oriented logic that interacts with external interfaces.
Key topics:
- Gigabit Ethernet
- FPGA communication interfaces
- High-throughput data movement
- Hardware/software communication
- FPGA-oriented network applications
This experiment focuses on using the FPGA's DDR3 external memory interface for data storage and retrieval.
Working with external DDR memory introduces a substantially different class of FPGA design problems compared with simple GPIO or serial interfaces, including memory-controller behavior, address/data movement, and reliable read/write operation.
Key topics:
- DDR3 memory
- FPGA external-memory interfaces
- Read/write transactions
- Data-path design
- Memory-oriented FPGA applications
PC_My_FPGA_PCIE_DMA_APP_Toolkit
This portion of the repository contains the PC-side application/toolkit associated with FPGA PCIe and DMA data transfer.
The directory includes a PCIe/DMA application structure together with supporting LabVIEW libraries.
Key topics:
- PCIe-based FPGA communication
- DMA data transfer
- Host-PC/FPGA interaction
- High-throughput data movement
- LabVIEW host-side tooling
This work complements the lower-level FPGA communication experiments by demonstrating the other half of an FPGA acceleration or data-acquisition system: the software running on the host PC.
A recurring theme across these projects was the complete FPGA development pipeline rather than only writing LabVIEW diagrams.
The workflow involved:
LabVIEW FPGA Design
│
▼
FPGA-oriented compilation / implementation
│
├── VHDL / EDF integration
│
▼
FPGA simulation
│
▼
Bitstream generation
│
▼
Artix-7 FPGA hardware
│
├── UART
├── Gigabit Ethernet
├── DDR3
└── PCIe / DMA
│
▼
Host PC Application
The repository also contains FPGA bitstream output and implementation artifacts, illustrating that the projects were not purely software simulations.
- AMD/Xilinx Artix-7
- Generic FPGA target rather than an NI-specific FPGA device
- Modified LabVIEW environment with support for generic FPGA targets
- LabVIEW FPGA programming model
- VHDL
- EDF-based FPGA implementation flow
- FPGA simulation
- FPGA bitstream generation
- UART / Serial
- Gigabit Ethernet
- DDR3
- PCIe
- DMA
- Host-PC communication
This training helped bridge the gap between graphical FPGA development and conventional RTL-oriented FPGA engineering.
In particular, I gained practical experience with:
- Designing FPGA functionality using LabVIEW's dataflow programming model.
- Understanding how high-level FPGA descriptions are translated into hardware implementations.
- Integrating externally generated or HDL-based logic into an FPGA project.
- Working with FPGA communication interfaces and external memory.
- Understanding the relationship between FPGA hardware and host-PC software.
- Working with generated simulation files and FPGA implementation artifacts.
- Deploying actual FPGA designs rather than restricting development to desktop LabVIEW applications.
The experience also gave me a useful perspective on the similarities and differences between LabVIEW FPGA, HDL-based RTL development, and more conventional FPGA vendor toolchains such as Vivado.
| Directory | Purpose |
|---|---|
实验4-串口通信实验 |
UART / serial communication experiments |
实验9-千兆以太网通信 |
Gigabit Ethernet communication |
实验29-DDR3内存读写实验 |
DDR3 memory read/write |
PC_My_FPGA_PCIE_DMA_APP_Toolkit |
PC-side PCIe/DMA application and supporting LabVIEW libraries |
FPGA Bitfiles |
Generated FPGA implementation/bitstream files |
A100.lvproj |
LabVIEW FPGA project |
A100.aliases |
LabVIEW target/alias configuration |
These projects were developed primarily as training and experimentation with a modified LabVIEW-to-FPGA workflow. The repository therefore contains generated files, implementation artifacts, simulation files, and project files alongside the LabVIEW source.
The purpose of the repository is to document the engineering workflow and FPGA concepts explored, rather than provide a polished standalone software package.
FPGA / RTL
- FPGA Design
- FPGA Implementation
- VHDL
- FPGA Simulation
- Bitstream Generation
- Digital Logic
- Memory Interfaces
Hardware Interfaces
- UART
- Gigabit Ethernet
- DDR3
- PCIe
- DMA
Software / Tools
- LabVIEW
- LabVIEW FPGA
- VHDL
- Vivado / FPGA implementation workflows
- Host-PC FPGA communication
This repository represents my transition from primarily software-oriented development toward hardware, FPGA, and digital-system development.
The work complemented my broader FPGA experience by exposing me to a different development ecosystem and, importantly, to the problem of using a high-level hardware-development environment to target a generic FPGA platform rather than a vendor-specific NI FPGA target.