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Feat/sve port avx53 - #232
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| static inline svuint32_t load_vec_sve(const void *addr) { | ||
| svuint32_t res; | ||
| /* asm 保证的加载 (core-179 配方要求; 全 VL 读, 存储侧用 pg4 截断) */ | ||
| __asm__ volatile ("ldr %0, [%1]" : "=w"(res) : "r"(addr) : "memory"); |
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On a 512-bit-or-wider SVE implementation, this ldr z reads svcntw() lanes even though the pg4 loop processes only four lanes at a time. In the final sub-block (sub == 1020), a 512-bit load reads through element 1035 while the buffers have only eight elements of slack (through 1031), causing out-of-bounds reads from the sources and temporary buffers. The same fixed +8 assumption is used by all four newly added arm0102_*_sve tests.
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| uint64_t phase[8]; | ||
| for (int k = 0; k < n; ++k) phase[k] = (base + k) % 4; | ||
| svuint64_t vphase = svld1_u64(pg, phase); |
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On SVE vector lengths above 512 bits, svcntd() makes n exceed eight (up to 32 lanes), so this loop writes past phase[8] before the predicate load consumes it. That corrupts the stack and makes the selected ALU operation for those lanes unreliable; the same pattern appears in the other newly added MRN and store-only variants, so those tests cannot run safely on wider SVE hardware.
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| uint8_t vidx_bytes[64]; | ||
| for (int i = 0; i < lanes && i < 16; ++i) | ||
| for (int b = 0; b < 4; ++b) | ||
| vidx_bytes[i * 4 + b] = (uint8_t)(i * 4 + idx4[b]); | ||
| svbool_t pg_batch = svwhilelt_b8((uint64_t)0, (uint64_t)(lanes < 16 ? lanes * 4 : 64)); |
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On a 1024-bit-or-wider SVE machine, svcntw() exceeds 16, but only the first 16 words' byte indices are initialized and loaded here. The active comparison still covers every lane, so svtbl produces incorrect bytes for the remaining lanes and deterministically enters the failure path; that path then stores n * 4 bytes into the same 64-byte round_bytes buffer. Build the index and diagnostic storage for the active vector length instead of capping them at 64 bytes.
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Conflict resolution: - README.md: keep main (drop PR-side count edits) - docs/docs_xu/README.md: keep main's removal (docs_xu/ consolidated into docs/superpowers/plans/ on main) - neon_rot_ldr_at_top_rowmajor_sve.cpp: keep PR side (superset — adds the cold-path bit dump on failure, FAIL#3 evidence gap) - tests/cpu/sve/meson.build: auto-merged (PR's batch 1-8 registrations + main's sve_sanitize_exempt flags; duplicate 3-line registration deduped) Verified: ninja clean build zero warnings; 484 tests listed (440+44); sampled new SVE tests + neon_rot_ldr_at_top_rowmajor_sve all pass; zstd19 -t 2000 -n 1 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com> Entire-Checkpoint: 01M4QV17C126GDGJJRHCEARKD2
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Conflict resolution: - README.md: keep main (drop PR-side count edits) - docs/docs_xu/README.md: keep main's removal (docs_xu/ consolidated into docs/superpowers/plans/ on main) - neon_rot_ldr_at_top_rowmajor_sve.cpp: keep PR side (superset — adds the cold-path bit dump on failure, FAIL#3 evidence gap) - tests/cpu/sve/meson.build: auto-merged (PR's batch 1-8 registrations + main's sve_sanitize_exempt flags; duplicate 3-line registration deduped) Verified: ninja clean build zero warnings; 484 tests listed (440+44); sampled new SVE tests + neon_rot_ldr_at_top_rowmajor_sve all pass; zstd19 -t 2000 -n 1 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
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Codex P1 (PR #232): the asm full-VL 'ldr z' in the last sub-block reads up to (COUNT-1)+svcntw() elements while the heap buffers carried only a fixed +8 slack — in-bounds at VL=256 (reads to 1027 of 1032), OOB from VL=512 (reads to 1035). Size the slack at runtime svcntw() in all four arm0102_*_sve tests (strictly sufficient for any VL/COUNT, per the movbe_slf_sweep VL-portable precedent). No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
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…e-only/u8x16 variants Codex P2 (PR #232): the phase scratch was a fixed 8-element (doubleword) / 64-byte (byte) stack array written with n = min(count-base, svcntd()/svcntb()) lanes — safe through VL=512 (svcntd=8), stack-OOB write from VL=1024 (svcntd=16 writes 16 into phase[8]) and from VL=1024 for the u8x16 byte variant (svcntb=128 > 64). Size all 12 newly added variants for the SVE architectural maximum VL of 2048 bits via SVE_MAX_VECTOR_BYTES (the movbe_slf_sweep VL-portable precedent); the macro needs a per-file fallback #define because openEuler's GCC 12 arm_sve.h does not provide this ACLE macro. No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
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…ive VL Codex P2 (PR #232): the byte-swap index table was initialized only for the first min(lanes,16) words and capped pg_batch at 64 bytes — on VL>=1024 (svcntw()>16) the tail lanes of vidx hold garbage bytes, which both corrupts the comparison (deterministic false failure) and, in the failure path, overflows the 64-byte round_bytes stack buffer and the 16-word round[] via svst1_u8/memcpy of n*4 bytes. Size vidx_bytes, round_bytes (SVE_MAX_VECTOR_BYTES) and round (SVE_MAX_VECTOR_BYTES/4) for the architectural max VL, drop the 16-word truncation and the pg_batch cap (movbe_l1d_vs_l2 + movbe_dump_golden, slf_sweep precedent; per-file SVE_MAX_VECTOR_BYTES fallback — GCC 12 arm_sve.h lacks it). No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
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…09 — L1D-hit vs L2-reload probe pair + init-golden-dump (3 tests) movbe_l1d_sve/movbe_l2_sve: the tested load is the asm-guaranteed svld1 reload of the heap input batch (svtbl [3,2,1,0] bswap round-trip); the l2 variant evicts every input cache line (dc civac + dsb sy) before the reload so it is served from L2/L3. movbe_dump_golden_sve: same round trip with init dumping the input buffer to /var/tmp (pid-suffixed, tmpfs-avoiding deviation from the scalar original's fixed /tmp path). Verified: ninja 458/458 zero new warnings; 3x 60s runs on --cpuset='!122' all 'exit: pass'; /var/tmp golden file 65536B; zstd19 regression pass; objdump shows ldr z reload + 2x tbl + st1b + cmpne in the hot loop. Entire-Checkpoint: 01M4JZN6EXF6ED3A8WNCW5Z7G3 Signed-off-by: wangxu <wangxumarshall@qq.com>
…1009 — fwd/l1d/diff/64k/1m/nop×6 (11 tests) fwd/l1d: the forwarding pair with the l1d variant evicting temp lines (dc civac + dsb sy, once per line) between svst1 and the asm ldr z. diff: different-address isolation (str tempA -> ldr tempB pre-filled with golden; asm pins the pair order); tempA same-value shared writes kept from the original with the safety argument documented. footprint: parameterized 64KB/1MB tempB scan (tag from test->id). nop battery: six delayed loads with .rept mov x9,x9 fused into the same asm block as the ldr z (compile-time counts, six distinct instantiations). Verified: ninja 462/462 zero new warnings; 11x 60s runs on --cpuset='!122' all 'exit: pass'; zstd19 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
…09 — nuke 2/3/4src + dense + pairs + reloaded (6 tests) Dependency-chain depth axis (2/3/4-source ALU chains, phase-predicate dispatch), the 16x load-density cell (16384 elements, golden=src), the pairs back-to-back collapse (code-identical to nuke_2src by original design, lineage documented), and the reloaded qword-segment variant (no dst, TEST_LOOP 1<<8, immediate vector compare + cold per-element rescan, asm ldr z reload). Verified: build zero new warnings; 6x 60s runs on --cpuset='!122' all 'exit: pass'; zstd19 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
…estcases_20261009 (4 tests)
agu_stress_store_only_sve: 2-src + {add,xor,and,OR} rotation, two stores
NO reload (original's OR-not-SUB rotation kept). neon_rot_store_only_sve:
the recipe minus the reload on z registers. neon_rot_u8x16_sve: full-VL
byte lanes (svcntb()/vector, 32 at VL=256) with per-byte phase and
asm-guaranteed temp reload — the width-vs-lane discriminator on SVE.
mem_disambig_alu_sve: svdup pattern stored/reloaded (asm ldr z) at random
data-dependent 8B-aligned offsets clamped to SIZE - lanes*8; VL
fail-closed.
Verified: build zero new warnings; 4x 60s runs on --cpuset='!122' all
'exit: pass'; zstd19 regression pass.
Signed-off-by: wangxu <wangxumarshall@qq.com>
…ases_20261009 — sub/mla/offdiag/str3/ldr4 (5 tests) sub: ALU-dimension rotation sub/eor/bic/orn (ORN composed as orr+not — no svorn in GCC 12 SVE1). mla: 32-bit MAC-lane rotation mul/mla/mls/eor with narrowed persisted sources. offdiag: source pair adjacent in one interleaved buffer (address-separation cell). str3: 3-store gradient cell (temp/junk/dst, dst-only blind spot kept for checkall). ldr4: 4-load gradient cell (2 dead scratch loads at top, rowmajor sweeps). Verified: build zero new warnings; 5x 60s runs on --cpuset='!122' all 'exit: pass'; zstd19 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
…s_20261009 — dump/gps/dualcmp/str3_checkall (4 tests) dump: per-element binary records (element-granular format, documented deviation from the scalar 16B lo/hi pairs) to /var/tmp + per-mismatch logs. gps: deterministic GPS self-describing tags (magic|byte_off| ~byte_off|gen) + five-buffer dump to movbe_log/gps_rowmajor (CWD-relative kept). dualcmp: both store legs checked + a_only/b_only/ab_div/ab_same classification. str3_checkall: 3-way slot mask + noinline cold scan + transient markers (index 0xFFFFFFFF). Verified: build zero new warnings (clangd pragma-pack warning confirmed ghost — GCC clean); 4x 60s runs on --cpuset='!122' all 'exit: pass'; zero fail records (all /var/tmp record files 0 bytes, no movbe_log fail dumps); zstd19 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
…ter_rand/k3res/k7p×4 (7 tests) k5far: srcA/srcB alternate VECTORS in one interleaved buffer (address neighbour always the other family) with GPS parity-magic tags + viewA/viewB-materialized dumps. k5inter_rand: same layout, natural random fill — the layout-vs-tag isolation control. k3res: 4096-slot 4x-footprint residency cell; byte_off tag field wraps at 64KB (complement of the wrapped value keeps the integrity check self-consistent; documented). k7pattern battery: zero/one/GPS-rand (deterministic tags, NOT memset_random — original naming)/hiham (0x55/0xAA by byte_off parity) sharing one implementation. Verified: build zero new warnings; 7x 60s runs on --cpuset='!122' all 'exit: pass'; zstd19 regression pass. Signed-off-by: wangxu <wangxumarshall@qq.com>
…ses_20261009 — select/not/logic/fma_f32 (4 tests) select: rotating BSL(a,b,b^a)/BSL(a,a,b)/BSL(a,b,a)/BSL(a,a&b,a^b) composed from svand/svnot/svorr (no svbsl in GCC 12 SVE1 ACLE). not: nand/nor/xnor/nandnot via svnot over and/or/eor/bic. logic: direct and/or/xor/bic mapping. fma_f32: 3-source (a, b, addend c) fma/fms/ fnma/fnms rotation with the neg-nested sequences kept verbatim; frandomf_scale(100.0f) lane fill. All on pg4 sub-blocks (NEON 4-lane semantics; svptrue at VL=256 would overrun) with +8-element buffer slack covering the asm full-VL ldr z at the final sub-block. Verified: build zero new warnings on the new files; 4x 60s runs on --cpuset='!122' all 'exit: pass'; zstd19 regression pass. Test count 406 -> 450 (all 44 ports registered). Signed-off-by: wangxu <wangxumarshall@qq.com>
… SVE ports (44 tests) README: --list-tests count 282 -> 450 (measured 2026-10-11) + a table row for the 44-test transfer-package port. docs_xu: full batch record (44-test table, eigen no-port verdict with evidence, the three porting idioms, 10 documented deviations from the scalar originals, per-batch verification records, issues caught in-flight) + index/progress-log entries (also lands the pending 9-22..9-24 index/log sync that was uncommitted in the working tree). Verification semantics corrected per 2026-10-11 user rulings (plan + docs): reliability = --cpuset=0-63 half-cores all-pass (!122 form RETIRED — 127 full cores squeeze daemons onto 122); effectiveness smoke = all cores incl. 122 observing REAL SDC; fault injection permanently dropped (this machine IS the SDC machine). Plan T10/T11 rewritten accordingly. Entire-Checkpoint: 01M4KAV1TJJP6B826T0JAE40BV Signed-off-by: wangxu <wangxumarshall@qq.com>
…vidence for missing_testcases SVE ports - T10: 44/44 pass on cores 0-63 (seq -s, expansion; cpuset range syntax unsupported) - T11.1: objdump SVE evidence 44/44 (own symbols 4-15, shared diff_fp 12, k7p common 13 via tail-jump wrappers) + regex erratum: \b(ldr\s+z|...)\b never matches 'ldr zN' (word boundary z/digit), fixed to ldr\s+z[0-9]+ - T11.2: all-core incl CPU122 smoke 07:24-08:08, 44/44 pass, no SDC triggered (122 online, re-capped 1.45GHz), zero other-core fail, kernel log clean - plan: check off T10/T11 steps; record verification-semantics rulings Entire-Checkpoint: 01M4M6HGNQ464F56W0NJBR6M51 Signed-off-by: wangxu <wangxumarshall@qq.com>
…instruction Launched 2026-10-11 08:45:38 via scripts/run/run-sve44-allcore-30min-20261011.sh (setsid nohup, death-tolerant STATUS.txt, rules-v2 fail detection, no -s random engine per run). Preflight passed: 122 online+MPIDR ok, cap 1.45GHz, 128 CPUs. ETA ~22h. Judgment: 122-only fail = effectiveness evidence; other-core fail = report for adjudication; crash/hang = stop and report. Signed-off-by: wangxu <wangxumarshall@qq.com>
…DC, 22h08m - BATCH_DONE 2026-10-12 06:53:58: pass=44 fail=0 signals-nosdc=0, active=wall=1328min no gaps (08:45:38 -> 06:53:58) - CPU122 online + 1.45GHz cap throughout (per-test recheck 44/44), boot_id unchanged (797e63a8) — 22h all-core load incl 122, zero machine anomaly (1.45+1.7GHz capped regime, hunt-v3 lineage) - Engines AES31/LCG13 random per run, seeds recorded, zero false positive - No trigger = chance principle (44 ported recipes are NOT the three lock-on tests; hunt v3 116 items/67h also triggered only probe_c) - Cumulative 122-inclusive test time ~113h; plan T12 checked off Entire-Checkpoint: 01M4QJMJZV56RK1MAP324Y0F0N Signed-off-by: wangxu <wangxumarshall@qq.com>
…n failure (FAIL#3 evidence gap) Signed-off-by: wangxu <wangxumarshall@qq.com>
Codex P1 (PR #232): the asm full-VL 'ldr z' in the last sub-block reads up to (COUNT-1)+svcntw() elements while the heap buffers carried only a fixed +8 slack — in-bounds at VL=256 (reads to 1027 of 1032), OOB from VL=512 (reads to 1035). Size the slack at runtime svcntw() in all four arm0102_*_sve tests (strictly sufficient for any VL/COUNT, per the movbe_slf_sweep VL-portable precedent). No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
…e-only/u8x16 variants Codex P2 (PR #232): the phase scratch was a fixed 8-element (doubleword) / 64-byte (byte) stack array written with n = min(count-base, svcntd()/svcntb()) lanes — safe through VL=512 (svcntd=8), stack-OOB write from VL=1024 (svcntd=16 writes 16 into phase[8]) and from VL=1024 for the u8x16 byte variant (svcntb=128 > 64). Size all 12 newly added variants for the SVE architectural maximum VL of 2048 bits via SVE_MAX_VECTOR_BYTES (the movbe_slf_sweep VL-portable precedent); the macro needs a per-file fallback #define because openEuler's GCC 12 arm_sve.h does not provide this ACLE macro. No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
…ive VL Codex P2 (PR #232): the byte-swap index table was initialized only for the first min(lanes,16) words and capped pg_batch at 64 bytes — on VL>=1024 (svcntw()>16) the tail lanes of vidx hold garbage bytes, which both corrupts the comparison (deterministic false failure) and, in the failure path, overflows the 64-byte round_bytes stack buffer and the 16-word round[] via svst1_u8/memcpy of n*4 bytes. Size vidx_bytes, round_bytes (SVE_MAX_VECTOR_BYTES) and round (SVE_MAX_VECTOR_BYTES/4) for the architectural max VL, drop the 16-word truncation and the pg_batch cap (movbe_l1d_vs_l2 + movbe_dump_golden, slf_sweep precedent; per-file SVE_MAX_VECTOR_BYTES fallback — GCC 12 arm_sve.h lacks it). No behavioral change at VL=256. Signed-off-by: wangxu <wangxumarshall@qq.com>
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Inline comments:
Review comments at @tests/cpu/sve/core179/movbe_dump_golden_sve.cpp:
- Line 173: Update the mismatch diagnostic in the test so its input field
reports the original value from in1 instead of repeating reload[k]. Keep
reload[k] as the value compared against the expected result.
Review comments at @tests/cpu/sve/core179/neon_rot_u8x16_sve.cpp:
- Line 135: Update the final iteration in the loop using load_vec_u8_sve and
store_vec_u8_sve so the full-vector load remains within the temp allocation:
retain the unpredicated load for complete chunks, and use a bounded tail load
for the partial chunk or ensure all buffers read by this helper have initialized
padding sufficient for the full load.
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📒 Files selected for processing (15)
docs/superpowers/plans/2026-10-10-missing-testcases-sve-port.mdtests/cpu/sve/core179/movbe_dump_golden_sve.cpptests/cpu/sve/core179/movbe_l1d_vs_l2_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_mla_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_dualcmp_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_gps_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k3res_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k5far_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k5inter_rand_sve.cpptests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k7pattern_sve.cpptests/cpu/sve/core179/neon_rot_u8x16_sve.cpptests/cpu/sve/kreg/arm0102_fma_f32_sve.cpptests/cpu/sve/kreg/arm0102_kreg_logic_sve.cpptests/cpu/sve/kreg/arm0102_kreg_not_sve.cpptests/cpu/sve/kreg/arm0102_kreg_select_sve.cpp
🚧 Files skipped from review as they are similar to previous changes (9)
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k5far_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_mla_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_gps_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k3res_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k5inter_rand_sve.cpp
- tests/cpu/sve/core179/movbe_l1d_vs_l2_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_dualcmp_sve.cpp
- tests/cpu/sve/core179/neon_rot_ldr_at_top_rowmajor_k7pattern_sve.cpp
- docs/superpowers/plans/2026-10-10-missing-testcases-sve-port.md
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added 2 commits
October 12, 2026 22:32
The dump-golden cold path printed reload[k] as both input and golden, so the log could not show whether the value loaded before the byte swap (in1) had already diverged from the tested reload. Preserve in1 and report it as input, keeping reload[k] as the comparison reference. Addresses CodeRabbit review comment 4249143898 on PR #232. Signed-off-by: wangxu <wangxumarshall@qq.com>
At a non-power-of-two SVE VL (e.g. 48 bytes), the final batch has n < svcntb() but load_vec_u8_sve() still issues an unpredicated full-vector `ldr z`, which reads up to svcntb() bytes past the 16,384-byte srcA/srcB/temp allocations. Give the buffers read by that helper a 256-byte slack (SVE architectural max VL) and zero temp's slack so the tail read stays in-bounds and initialized at any VL. The hot-loop instruction sequence is unchanged. Addresses CodeRabbit review comment 4249143905 on PR #232. Signed-off-by: wangxu <wangxumarshall@qq.com>
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…essages (11 tests) Signed-off-by: wangxu <wangxumarshall@qq.com>
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Emit the two-line YAML message log_yaml(char, const char*) requires; the single-line histogram tripped the parser assert on debugoptimized builds. Signed-off-by: wangxu <wangxumarshall@qq.com>
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added 2 commits
October 13, 2026 00:29
fcmla_golden_pair() switched on the rotation angle (0/90/180/270) while every caller passed the loop index 0..3, so rotations 1..3 all took the 270-degree default branch. The one-step self-check then failed at rot 90 (CI: 'golden worked-example self-check failed (rot 90)') and the chain golden was built with the wrong rotation. Switch on the index to match the callers and the hardware dispatch (fcmla_hw_rot*). Signed-off-by: wangxu <wangxumarshall@qq.com>
…erge ACLE svmla_f64_x(pg, a, b, c) is a + b*c, but the test passed vsrc as the accumulator (vsrc + vsrc*vdst), so active-lane results never matched the fma(src,src,...) golden and masked-out lanes were clobbered instead of preserved (the _x form leaves inactive lanes unspecified). Accumulate into the destination and use the merging _m form (op1 + op2*op3) with a finite addend on the active lanes and the NaN sentinel on the inactive ones, making the sentinel check sound. Same fix in the timed re-loop. Signed-off-by: wangxu <wangxumarshall@qq.com>
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Section 4 read the First Fault Register with svrdffr() without priming it first. Per the ARM SVE first-fault model an LDFF1 only *clears* the FFR bit of a faulting element, it never *sets* a bit, so the readback was the previous (undefined) FFR state rather than the set of loaded lanes. On the CI runner (VL=128) that state was 0, so svcntp_b64 reported count=0 instead of the expected 2 and the test failed its own golden. Call svsetffr() immediately before the svldff1_f64 so every non-faulting lane's FFR bit is the architecturally defined 1. Verified on the local GCC 12 aarch64 toolchain: GCC emits a real ldff1d (no relaxation to ld1) and emits setffr only when svsetffr() is present. Signed-off-by: wangxu <wangxumarshall@qq.com> Signed-off-by: wangxumarshall <wangxumarshall@qq.com>
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Signed-off-by: wangxu <wangxumarshall@qq.com> Entire-Checkpoint: 01M4RGAQECNGXEZCX2M4285KDP
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Signed-off-by: wangxu <wangxumarshall@qq.com>
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…tests) Signed-off-by: wangxumarshall <wangxumarshall.0104@qq.com>
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Signed-off-by: wangxumarshall <wangxumarshall.0104@qq.com>
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added 2 commits
October 13, 2026 02:57
…cords (11 tests) Signed-off-by: wangxumarshall <wangxumarshall.0104@qq.com> Entire-Checkpoint: 01M4RQKRJQGBKR9PQTAYJV062Q
…s fail-dump idiom (6 tests + docs) Signed-off-by: wangxumarshall <wangxumarshall.0104@qq.com> Entire-Checkpoint: 01M4RQKWR7JH0FSBHPVMTW44KW
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…mpanion to 0d040a3) Signed-off-by: wangxumarshall <wangxumarshall.0104@qq.com> Entire-Checkpoint: 01M4RQP3REAZ7RAES627DDV31B
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变更说明
自验证清单(CLAUDE.md 规则 2,100% 实证)
ninja -C builddir干净构建,零新增告警./builddir/sdcshield -e zstd19 -t 2000 -n 1→exit: passEXIT_SKIP+ placeholder 理由跳过,无假通过提交卫生
git commit -s(Signed-off-by 为最后一行)Summary by CodeRabbit
New Features
Bug Fixes
Documentation
Testing