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Bump inclusive LLC for sbus-cbus clocking fix #2364

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Bump inclusive LLC for sbus-cbus clocking fix #2364

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7 changes: 7 additions & 0 deletions generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,13 @@ class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = In
case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
})

// Customize the control crossing of the inclusive LLC. The LLC runs on the sbus domain, and the
// two control ports are driven by the cbus. Defaults to whatever crossing is already configured
// between sbus and cbus.
class WithInclusiveCacheCtrlCrossingType(xType: Option[ClockCrossingType] = None) extends Config((site, here, up) => {
case InclusiveCacheKey => up(InclusiveCacheKey).copy(ctrlXType = xType.getOrElse(site(SbusToCbusXTypeKey)))
})

/** Use asynchronous reset for Rocket Chip's Debug Module. */
class WithAsyncResetRocketSubsystem extends Config((_, _, _) => {
case SubsystemResetSchemeKey => ResetAsynchronous
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2 changes: 1 addition & 1 deletion generators/rocket-chip-inclusive-cache
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Submodule rocket-chip-inclusive-cache updated 1 files
+11 −4 design/craft/inclusivecache/src/Configs.scala