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1. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala

2. riscv-arch-test riscv-arch-test Public

   Forked from riscv/riscv-arch-test

   The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.

   Assembly

3. rocket-chip-inclusive-cache rocket-chip-inclusive-cache Public

   Forked from chipsalliance/rocket-chip-inclusive-cache

   An RTL generator for a last-level shared inclusive TileLink cache controller

   Scala