Hardware implementation of a Double Pulse Test (DPT) platform for SiC MOSFETs. Features LTspice parasitic modeling, ANSYS Q3D extraction, and a novel 4-layer Vertical Multi-Loop PCB layout that minimizes parasitic inductance and switching losses for high-frequency wide-bandgap applications.
pcb-layout power-electronics ansys altium-designer ltspice hardware-design sic-mosfet double-pulse-test wide-bandgap-semiconductors
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Updated
Aug 14, 2026