traffic-controller

Project done for my B.Tech course on Formal Methods for System Verification

FSM-based traffic light controller implemented in Verilog with timed state transitions and an emergency-response override flag for priority handling. Designed for synchronous control and real-time traffic management logic.

Sensor-aware 4-road traffic light controller using Finite State Machine in Verilog. Dynamically manages traffic flow with priority-based signal allocation, timer-controlled phase transitions, and real-time traffic monitoring for smart city applications.

AI-driven models can predict congestion and optimize signal timings dynamically, improving traffic movement. Combining these predictions with FPGA-based real-time control enables fast, reliable, and intelligent traffic management for modern smart cities.

Scaled 2-way Hardware-in-the-Loop (HIL) traffic signal controller built on Arduino UNO with non-blocking logic and Emergency Vehicle Preemption (EVP).

FSM-based traffic light controller designed and verified using Verilog HDL and Vivado.

RTL design of a T-shaped Traffic Management System using Verilog HDL.

Design and FPGA implementation of a starvation-free adaptive priority traffic controller using Verilog HDL.

Simulating traffic controller sequence at Thapathali intersection using Xilinx and 8051

State machine based smart traffic controller using Arduino and Wokwi