Passionate about RTL Design, Functional Verification, and Digital IC Design. I enjoy designing digital systems using Verilog/SystemVerilog and verifying them using UVM while continuously exploring ASIC design methodologies.

• M.Tech in VLSI
• Interested in RTL Design, Functional Verification, and ASIC Design
• Working with Verilog, SystemVerilog, and UVM
• Passionate about Digital Design and Verification
• Currently learning advanced ASIC Design and Verification methodologies

M.Tech in VLSI
Amity University, Noida
2025 – 2027

B.Tech in Electronics and Communication Engineering
Dayananda Sagar University, Bengaluru
2021 – 2025

• Verilog
• SystemVerilog

• Universal Verification Methodology (UVM)
• Testbench Development
• Functional Verification

• Xilinx Vivado
• Siemens Questa
• Synopsys VCS
• Synopsys Design Compiler
• LTspice
• NGSpice

• C
• C++
• Python

• RTL design and functional verification of an intelligent traffic management system using SystemVerilog and UVM.
• Features include traffic signal control, emergency vehicle priority, traffic violation detection, and PUC approval logic.

• Designed and implemented a T-junction traffic controller using Verilog HDL.
• Verified functionality through simulation using a finite state machine (FSM)-based approach.

• Developed a UVM testbench to verify a 4-bit adder.
• Implemented driver, monitor, scoreboard, sequences, and functional coverage.

• Designed a Verilog HDL-based water level detection system with simulation and verification.

• Designed and simulated a full-wave bridge rectifier battery charger using LTspice and NGSpice.
• Implemented Zener diode-based voltage regulation and analyzed circuit performance through simulation.

• Designed and simulated a DC-DC Buck Converter using LTspice for voltage regulation analysis.

• Developed a smart home automation and assistance system using ARM and Microsoft Kinect.

• VLSI Training (Level 1 & Level 2) – ISWDP (Synopsys) (2024)
• NPTEL Certification – Design for Testability (2024)
• Summer School on "Silicon to System" – CREST, BITS Pilani Hyderabad Campus (2025)
• Hands-on Training in LTspice & NGSpice – Amity University (2026)
• VLSI Training & Internship – LaunchED Global (2026)
• VLSI Training & Internship Program – Indian Institute of Science (IISc), Bengaluru (2026)

• RTL Design using Verilog & SystemVerilog
• Functional Verification using UVM
• ASIC Design Flow
• FPGA-Based Digital System Design
• Digital IC Design

• LinkedIn: Chinmay G Bhat
• Email: chinmay.advaitham@gmail.com

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