Reverse engineering NVIDIA SASS instruction dictionary, kernel audits and pattern recognition across GPU architectures.
The R package for SVM with GPU architecture based on the GTSVM software
CUDA C simple application for Nvidia's GPU
SIMT GPU warp execution simulator tracking active thread divergence masks, reconvergence points, and warp vote intrinsics (__ballot_sync, __all_sync, __any_sync).
SIMT GPU warp execution simulator tracking active thread divergence masks, reconvergence points, and warp vote intrinsics (__ballot_sync, __all_sync, __any_sync).
📚 grimoire: Textbooks of magic for computer scientists. Permanently free.
A minimal SystemVerilog implementation of a GPGPU architecture. Features a custom ISA, SIMD execution model, and matrix operation kernels with a robust simulation and verification framework using Cocotb
This tutorial was presented at the winter school in Deep Learning at UiT [13/01/2023] (see https://www.nldl.org/winter-school).
SPPU BE in Computer Engineering 2019 Pattern Semester 7 Lab Assignments
A plain-spoken, interactive course on NVIDIA's Blackwell architecture — the chips, engines, and rack-scale systems built for the age of AI reasoning.
Understanding GPU architecture for AI, from CUDA execution and memory to performance and production systems.
Four-warp, eight-lane programmable SIMT processor with scoreboarding, divergence, banked memory, differential verification, and an ASIC RTL-to-GDS flow.
Progressive CUDA SGEMM kernel(6) optimization (naive → vectorized) with cross-architecture profiling on RTX 3090 vs RTX 4050, benchmarked using Nsight Compute.
CPEN 311: Digital Systems Design
Python-based simulation of a GPGPU architecture, emulating Streaming Multiprocessors (SMs) and thread-level parallelism for high-performance computing (HPC)
GPU Performance: GEMM, GEMV and GRAM costing across gpu architecture
[Tasks] A collection of homework tasks, projects given during Chaos Camp 2025 Course
Roofline analysis of BitNet b1.58 2B4T inference across H100, MI300X, Groq LPU, Cerebras WSE-3, and two hypothetical ternary chips. Five phases covering gate counts, precision sweeps, memory bandwidth, hybrid activation Pareto, and prefill regime, plus empirical weight-distribution validation against the published microsoft/bitnet weights.
Interactive, scroll-driven visualization of NVIDIA H100 architecture, connecting GPU hardware with CUDA, Triton, and PyTorch programming concepts.
To associate your repository with the gpu-architecture topic, visit your repo's landing page and select "manage topics."