arty-z7

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francdoc / fpga-temporal-reuse

A controlled Arty Z7-10 FPGA experiment comparing repeated BRAM reads with register reuse, with reproducible simulation, hardware checks and power estimates.

fpga vhdl vivado computer-architecture zynq-7000 arty-z7 temporal-reuse

Updated Sep 27, 2026
VHDL

metebalci / muir-fpga

Star

The MIT CADR Lisp Machine on an FPGA

fpga zynq amd xilinx vivado altera lisp-machine verilator quartus zynq-7020 cadr cora-z7 agilex arty-z7 kria-kr260 agilex5 de25-nano zynq-ultrascale-plus quux

Updated Oct 28, 2026
SystemVerilog

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