zynq-7000

Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API

一个开源的FPGA神经网络加速器。

This is xc7z020clg400 FPGA hardware core board design

Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP

Dual-Mode PSK Transceiver on SDR With FPGA

Kicad design files for a Zynq 7020 SoM

Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)

FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD

This is 8 channels BISS-C FPGA hardware board design

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

AXI support for Migen/MiSoC

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

Implementation of a VGA Controller in Verilog (Both Graphics Mode and Text Mode)

KVM over IP Gateway targeting Zynq-7000 SoC

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

Native Rust support for AMD Zynq 7000 SoC bare-metal programming

Global Dark Mode for ALL apps on ANY platforms.

4-Layer XC7Z010 DDR3 Layout