update target for gt2n

lambdapdk/gt2n/target.py

@@ -1,7 +1,11 @@
 # Import necessary classes from the siliconcompiler framework and the LambdaPDK.
+from typing import Optional
+
 from siliconcompiler import ASIC
 from siliconcompiler.flows import asicflow, synflow
 
+from siliconcompiler.targets._utils import detect_elaboration_language
+
 from lambdapdk.gt2n.libs.stdcells import GT2N6TW31LVT, GT2N6TW31HVT, GT2N6TW31SVT, GT2N6TW31ULVT, \
     GT2N6TW31ELVT
 
@@ -13,7 +17,8 @@ def gt2n_demo(
         project: ASIC,
         syn_np: int = 1,
         floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
-        timing_np: int = 1):
+        timing_np: int = 1,
+        language: Optional[str] = None):
     """
         Configure a siliconcompiler ASIC for the GT2N.
 
@@ -31,6 +36,8 @@ def gt2n_demo(
             * route_np (int): Parallelism for routing.
             * timing_np (int): Parallelism for timing analysis (synthesis-only flow).
         """
+    if language is None:
+        language = detect_elaboration_language(project)
 
     # 1. Load Standard Cell Library
     # Sets the primary standard cell library for the design. This library
@@ -48,10 +55,12 @@ def gt2n_demo(
         floorplan_np=floorplan_np,
         place_np=place_np,
         cts_np=cts_np,
-        route_np=route_np))
+        route_np=route_np,
+        language=language))
     project.add_dep(synflow.SynthesisFlow(
         syn_np=syn_np,
-        timing_np=timing_np))
+        timing_np=timing_np,
+        language=language))
 
     # 3. Set Target PDK
     # Specifies the process development kit to be used.