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SMALLFIX: Fix Liberty writer for slash and dollar bus names #464

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SMALLFIX: Fix Liberty writer for slash and dollar bus names #464

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2 changes: 1 addition & 1 deletion liberty/LibertyLex.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ HNAME ({PIN_NAME}|{BUS_NAME}|{MIXED_NAME})([\/.]({PIN_NAME}|{BUS_NAME}|{MIXED_NA
/* default_operating_conditions : slow_100_3.00 ; */
/* revision : 1.0.17; */
/* default_wire_load : xc2v250-5_avg; */
TOKEN ({ALPHA}|{DIGIT}|_)({ALPHA}|{DIGIT}|[._\-])*(:({ALPHA}|{DIGIT}|_)+)?
TOKEN ({ALPHA}|{DIGIT}|_|\$)({ALPHA}|{DIGIT}|[._\-$])*(:({ALPHA}|{DIGIT}|_)+)?
/* bus_naming_style : %s[%d] ; */
BUS_STYLE "%s"{BUS_LEFT}"%d"{BUS_RIGHT}
PUNCTUATION [,\:;|(){}+*&!'=]
Expand Down
42 changes: 32 additions & 10 deletions liberty/LibertyWriter.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@
#include <cstdlib>
#include <fstream>
#include <string>
#include <string_view>

#include "Error.hh"
#include "Format.hh"
Expand Down Expand Up @@ -93,6 +94,27 @@ class LibertyWriter
const Unit *cap_unit_;
};


static std::string
portStaToLiberty(std::string_view sta_name)
{
std::string liberty_name;
for (size_t i = 0; i < sta_name.length(); i += 1) {
char ch = sta_name[i];
if (ch == '\\') {
char next_ch = sta_name[i + 1];
if (next_ch == '\\') {
liberty_name += ch;
liberty_name += next_ch;
i++;
}
}
else
liberty_name += ch;
}
return liberty_name;
}

void
writeLiberty(LibertyLibrary *lib,
const char *filename,
Expand Down Expand Up @@ -272,7 +294,7 @@ LibertyWriter::writeBusDcls()
{
BusDclSeq dcls = library_->busDcls();
for (BusDcl *dcl : dcls) {
sta::print(stream_, " type (\"{}\") {{\n", dcl->name());
sta::print(stream_, " type (\"{}\") {{\n", portStaToLiberty(dcl->name()));
sta::print(stream_, " base_type : array;\n");
sta::print(stream_, " data_type : bit;\n");
sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to()) + 1);
Expand All @@ -295,7 +317,7 @@ LibertyWriter::writeCells()
void
LibertyWriter::writeCell(const LibertyCell *cell)
{
sta::print(stream_, " cell (\"{}\") {{\n", cell->name());
sta::print(stream_, " cell (\"{}\") {{\n", portStaToLiberty(cell->name()));
float area = cell->area();
if (area > 0.0)
sta::print(stream_, " area : {:.3f} \n", area);
Expand Down Expand Up @@ -333,9 +355,9 @@ LibertyWriter::writeCell(const LibertyCell *cell)
void
LibertyWriter::writeBusPort(const LibertyPort *port)
{
sta::print(stream_, " bus(\"{}\") {{\n", port->name());
sta::print(stream_, " bus(\"{}\") {{\n", portStaToLiberty(port->name()));
if (port->busDcl())
sta::print(stream_, " bus_type : {};\n", port->busDcl()->name());
sta::print(stream_, " bus_type : \"{}\";\n", portStaToLiberty(port->busDcl()->name()));
writePortAttrs(port);

LibertyPortMemberIterator member_iter(port);
Expand All @@ -349,7 +371,7 @@ LibertyWriter::writeBusPort(const LibertyPort *port)
void
LibertyWriter::writePort(const LibertyPort *port)
{
sta::print(stream_, " pin(\"{}\") {{\n", port->name());
sta::print(stream_, " pin(\"{}\") {{\n", portStaToLiberty(port->name()));
writePortAttrs(port);
sta::print(stream_, " }}\n");
}
Expand All @@ -362,18 +384,18 @@ LibertyWriter::writePortAttrs(const LibertyPort *port)
if (func
// cannot ref internal ports until sequentials are written
&& !(func->port() && func->port()->direction()->isInternal()))
sta::print(stream_, " function : \"{}\";\n", func->to_string());
sta::print(stream_, " function : \"{}\";\n", portStaToLiberty(func->to_string()));
auto tristate_enable = port->tristateEnable();
if (tristate_enable) {
if (tristate_enable->op() == FuncExpr::Op::not_) {
FuncExpr *three_state = tristate_enable->left();
sta::print(stream_, " three_state : \"{}\";\n",
three_state->to_string());
portStaToLiberty(three_state->to_string()));
}
else {
FuncExpr *three_state = tristate_enable->copy()->invert();
sta::print(stream_, " three_state : \"{}\";\n",
three_state->to_string());
portStaToLiberty(three_state->to_string()));
delete three_state;
}
}
Expand All @@ -400,7 +422,7 @@ LibertyWriter::writePortAttrs(const LibertyPort *port)
void
LibertyWriter::writePwrGndPort(const LibertyPort *port)
{
sta::print(stream_, " pg_pin(\"{}\") {{\n", port->name());
sta::print(stream_, " pg_pin(\"{}\") {{\n", portStaToLiberty(port->name()));
sta::print(stream_, " pg_type : \"{}\";\n", pwrGndTypeName(port->pwrGndType()));
sta::print(stream_, " voltage_name : \"{}\";\n", port->voltageName());
sta::print(stream_, " }}\n");
Expand All @@ -426,7 +448,7 @@ LibertyWriter::writeTimingArcSet(const TimingArcSet *arc_set)
{
sta::print(stream_, " timing() {{\n");
if (arc_set->from())
sta::print(stream_, " related_pin : \"{}\";\n", arc_set->from()->name());
sta::print(stream_, " related_pin : \"{}\";\n", portStaToLiberty(arc_set->from()->name()));
TimingSense sense = arc_set->sense();
if (sense != TimingSense::unknown && sense != TimingSense::non_unate)
sta::print(stream_, " timing_sense : {};\n", to_string(sense));
Expand Down
111 changes: 111 additions & 0 deletions test/liberty_write_escaped_names.lib
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@@ -0,0 +1,111 @@
library (liberty_write_escaped_names) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);

input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 30;
slew_lower_threshold_pct_fall : 30;
slew_upper_threshold_pct_rise : 70;
slew_upper_threshold_pct_fall : 70;
slew_derate_from_library : 1.0;


nom_process : 1.0;
nom_temperature : 85.0;
nom_voltage : 0.75;

type ("$vol_ts_new") {
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 1;
bit_to : 0;
}

type ("div/u_div/QInv") {
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 1;
bit_to : 0;
}

cell ("my_buf") {
pin("u_sub/data[0]") {
direction : input;
capacitance : 1.0000;
}
bus("div/u_div/QInv") {
bus_type : div/u_div/QInv;
direction : output;
capacitance : 0.0000;
pin("div/u_div/QInv[1]") {
direction : output;
capacitance : 0.0000;
timing() {
related_pin : "u_sub/data[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(scalar) {
values("1.00000");
}
rise_transition(scalar) {
values("1.00000");
}
cell_fall(scalar) {
values("1.00000");
}
fall_transition(scalar) {
values("1.00000");
}
}
}
pin("div/u_div/QInv[0]") {
direction : output;
capacitance : 0.0000;
timing() {
related_pin : "u_sub/data[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(scalar) {
values("1.00000");
}
rise_transition(scalar) {
values("1.00000");
}
cell_fall(scalar) {
values("1.00000");
}
fall_transition(scalar) {
values("1.00000");
}
}
}
}
bus("$vol_ts_new") {
bus_type : $vol_ts_new;
direction : output;
capacitance : 0.0000;
pin("$vol_ts_new[1]") {
direction : output;
capacitance : 0.0404;
}
pin("$vol_ts_new[0]") {
direction : output;
capacitance : 0.0411;
}
}
}

}
110 changes: 110 additions & 0 deletions test/liberty_write_escaped_names.ok
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@@ -0,0 +1,110 @@
library (liberty_write_escaped_names) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);

input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 30;
slew_lower_threshold_pct_fall : 30;
slew_upper_threshold_pct_rise : 70;
slew_upper_threshold_pct_fall : 70;
slew_derate_from_library : 1.0;


nom_process : 1.0;
nom_temperature : 85.0;
nom_voltage : 0.75;

type ("$vol_ts_new") {
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 1;
bit_to : 0;
}
type ("div/u_div/QInv") {
base_type : array;
data_type : bit;
bit_width : 2;
bit_from : 1;
bit_to : 0;
}

cell ("my_buf") {
pin("u_sub/data[0]") {
direction : input;
capacitance : 1.0000;
}
bus("div/u_div/QInv") {
bus_type : "div/u_div/QInv";
direction : output;
capacitance : 0.0000;
pin("div/u_div/QInv[1]") {
direction : output;
capacitance : 0.0000;
timing() {
related_pin : "u_sub/data[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(scalar) {
values("1.00000");
}
rise_transition(scalar) {
values("1.00000");
}
cell_fall(scalar) {
values("1.00000");
}
fall_transition(scalar) {
values("1.00000");
}
}
}
pin("div/u_div/QInv[0]") {
direction : output;
capacitance : 0.0000;
timing() {
related_pin : "u_sub/data[0]";
timing_sense : positive_unate;
timing_type : combinational;
cell_rise(scalar) {
values("1.00000");
}
rise_transition(scalar) {
values("1.00000");
}
cell_fall(scalar) {
values("1.00000");
}
fall_transition(scalar) {
values("1.00000");
}
}
}
}
bus("$vol_ts_new") {
bus_type : "$vol_ts_new";
direction : output;
capacitance : 0.0000;
pin("$vol_ts_new[1]") {
direction : output;
capacitance : 0.0404;
}
pin("$vol_ts_new[0]") {
direction : output;
capacitance : 0.0411;
}
}
}

}
3 changes: 3 additions & 0 deletions test/liberty_write_escaped_names.tcl
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@@ -0,0 +1,3 @@
# Verify write_liberty round-trips pin names containing / and []
read_liberty liberty_write_escaped_names.lib
sta::write_liberty [get_libs liberty_write_escaped_names] results/liberty_write_escaped_names.log
1 change: 1 addition & 0 deletions test/regression_vars.tcl
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Expand Up @@ -156,6 +156,7 @@ record_public_tests {
liberty_ccsn
liberty_float_as_str
liberty_latch3
liberty_write_escaped_names
make_concrete_parasitics_leak
package_require
path_group_names
Expand Down