test: cover event generator IRQ 11 FIFO path

[shivamtiwari020505]

Summary

• Add a self-checking regression for events 7 and 8 through the FC FIFO and IRQ 11 path.
• Add a reusable FuseSoC event-generator-test target with Verilator and Icarus support.
• Clarify that fc_events_o[1:0] is a separate unused direct-output path.
• Document that CPU IRQ 11 acknowledgment captures and pops the FIFO entry before software reads REG_FIFO.

Rationale

Investigation of issue #355 found that events 7 and 8 already enter the normal FC arbitration and FIFO path when their FC mask bits are cleared.

The separate fc_events_o[1:0] output mirrors these events directly but has no downstream consumer in CORE-V-MCU. Connecting that output to IRQ 11 would bypass the event mask and FIFO event-ID semantics.

This PR adds regression coverage and documentation without changing the RTL interrupt map or existing software behavior.

Testing

• FuseSoC event-generator-test with Verilator
• FuseSoC event-generator-test with Icarus
• Full FuseSoC Verilator lint target
• Sphinx HTML documentation build
• Git whitespace validation

Related to #355.

[Copilot]

Pull request overview

This PR adds regression coverage and documentation around the APB event controller’s FC FIFO / CPU IRQ 11 delivery path, specifically validating that events 7 and 8 are delivered via the masked FIFO semantics (and not via the separate direct fc_events_o[1:0] mirror output).

Changes:

• Added a self-checking SystemVerilog testbench that verifies masking behavior, FIFO event ID capture timing, IRQ 11 acknowledgment semantics, and simultaneous delivery of events 7/8.
• Added a reusable FuseSoC target (event-generator-test) to run the event-generator regression with Verilator or Icarus.
• Updated documentation and TB README guidance to clarify the unused direct-output path and to document the IRQ 11/FIFO CSR capture/pop behavior.

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 1 comment.

File	Description
tb/soc_event_generator_tb.sv	New self-checking regression test for events 7/8 through the FC FIFO and IRQ 11 path
tb/README.md	Adds instructions for running the new FuseSoC regression target
docs/doc-src/ip-blocks/apb_event_cntrl.rst	Clarifies FC direct-output vs FIFO-based IRQ 11 path and documents FIFO CSR capture timing
core-v-mcu.core	Adds a new FuseSoC fileset/target to build and run the regression under Verilator/Icarus

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[MikeOpenHWGroup]

I really like this contribution @shivamtiwari020505 and I would like to suggest we organize it to better reflect the its focus.

The top-level tb/ directory is intended to be a testbench for the top-level of the CORE-V-MCU and integrating a unit test-bench for a single module will confuse things (imagine if the all the modules has a unit test-bench in the tb/ directory and the core-v-mcu.core FuseSoC file was intended to support them all. So I suggest that we model the organization of the soc_event_generator after the rtl/udma/udma_i2c/ model to look something like this:

rtl/core-v-mcu/soc/soc_event_generator               # New directory
                     ├── rtl
                     │   └── soc_event_generator.sv  # existing RTL module
                     ├── src_files.yml               # optional (not sure it is necessary in this case)
                     ├── tb
                     │   ├── README.md
                     │   ├── Makefile                # "nice to have"
                     │   ├── ... any other testbench files
                     │   └── soc_event_generator_tb.sv
                     └── soc_event_generator.core

The location of docs/doc-src/ip-blocks/apb_event_cntrl.rst is good (please have a look at the comment by Copilot about the indentation of the restructured text.

[MikeOpenHWGroup]

Thanks for this @shivamtiwari020505, LTGM. I am approving these changes, but will not merge until @cst-aditya has a chance to comment (they made the previous update to apb_event_cntrl.rst).

[shivamtiwari020505]

Understood, Mike. I’ll wait for @cst-aditya to review the documentation update and will address any feedback they may have.

[cst-aditya]

Hi @MikeOpenHWGroup, @shivamtiwari020505

I reviewed the updates in apb_event_cntrl.rst and they look good to me.

[MikeOpenHWGroup]

Thanks @cst-aditya. I will merge this in.