RTL & Digital Design | ASIC/FPGA | Verification
I build and verify synthesizable digital hardware using Verilog, SystemVerilog, and Python-based verification. My interests include reusable RTL IP, microarchitecture, FPGA/ASIC implementation, and open-silicon development.
- OpenHW Group / CORE-V MCU - Added a self-checking regression for events 7 and 8 through the FC FIFO and IRQ 11 path, a reusable FuseSoC test target for Verilator and Icarus, and supporting documentation. Merged.
- OpenHW Group / CORE-V MCU - Connected the uDMA I2C status-event path through clock-domain crossing, sticky status registers, and SoC event routing; added focused RTL tests and documentation. Merged.
- YosysHQ / SymbiYosys - Documented the
prepmode and relatedskip_prepoption. Merged.
