UART Transmitter using Verilog HDL

Overview

This project implements a UART (Universal Asynchronous Receiver Transmitter) using Verilog HDL. The transmitter converts 8-bit parallel data into serial data using a Finite State Machine (FSM).

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Features

• FSM based UART Transmitter
• 8-bit Serial Data Transmission
• Start Bit and Stop Bit Generation
• Shift Register based Data Transfer
• Bit Counter
• Verilog Testbench
• Functional Verification

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FSM States

IDLE → START → DATA → STOP → IDLE

State	Function
IDLE	Wait for transmission
START	Send start bit (0)
DATA	Send 8 data bits
STOP	Send stop bit (1)

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Project Structure

UART-Transmitter/
│
├── src/
├── tb/
├── waveform/
├── block_diagram/
├── state_diagram/
└── README.md

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Block Diagram

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FSM State Diagram

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Simulation Waveform

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Tools Used

• Verilog HDL
• VS Code
• Icarus Verilog
• EDA Playground / EPWave
• Git
• GitHub

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Simulation Commands

Compile

iverilog -o uart src/uart_tx.v tb/uart_tx_tb.v

Run

vvp uart

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Author

Developed as a VLSI RTL Design Project.