Light-sleep CPU/TOP power-down for ESP32-C6 and ESP32-H2 - #5874
Light-sleep CPU/TOP power-down for ESP32-C6 and ESP32-H2#5874JurajSadel wants to merge 8 commits into
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What's the plan with this PR, is this ever coming out of draft? |
| // I2C: ESP-IDF v5.4 `i2c_periph.c` `i2c0_regs_retention`, `i2c_reg.h`. | ||
| pub(super) const I2C_SCL_LOW_PERIOD_OFF: u32 = 0x00; // I2C_SCL_LOW_PERIOD_REG: ADDR_MAP window base | ||
| pub(super) const I2C_CTR_OFF: u32 = 0x04; // I2C_CTR_REG | ||
| pub(super) const I2C_FSM_RST: u32 = 1 << 10; // I2C_FSM_RST (value == mask) | ||
| pub(super) const I2C_CONF_UPGATE: u32 = 1 << 11; // I2C_CONF_UPGATE (value == mask) | ||
| /// Registers retained (set bits in [`I2C_REGS_MAP`]). | ||
| pub(super) const I2C_RETENTION_REGS_CNT: u32 = 18; | ||
| /// `i2c0_regs_map[4]`: config registers in the `SCL_LOW_PERIOD..SCL_STRETCH_CONF` window. | ||
| pub(super) const I2C_REGS_MAP: [u32; 4] = [0xc03f_345b, 0x3, 0, 0]; |
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I am annoyed by this. We're defining a bunch of constants, so that common code can build up a presumed-common chain of operations for a peripheral. What we really want, is a per-chip, per-peripheral operation chain, just like the sys operations are. Nothing ensures peripherals have the same shape.
Also, I'd prefer, however long, explicitly spelling out the registers we back up. That binary map is impossible to read or write.
| count: 18, | ||
| }, // HP_SYSTEM ..= HP_SYSTEM_MEM_TEST_CONF_REG (+0x44) | ||
| // PRI_5: console UART0. | ||
| Uart { base: 0x6000_0000 }, |
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Annoying. IDK what we should do about UART0 and SYSTIMER. SYSTIMER can be considered a system peripheral I guess, but we can also just reconfigure it fully on wakeup, we don't necessarily need to save it. UART is annoying because the user may not even be using it for println, so we likely just waste time and memory, but if they do use it, it needs to be saved. Once we resolve #4666 I guess it needs to be configured separately, but then we'll make it easy to configure half of the system only :(
| }; | ||
| } | ||
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| noncritical_csrs! { |
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We should use the riscv(-rt?) CSR access functions, and we should define the missing registers in esp-riscv-rt.
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| [target.'cfg(target_arch = "riscv32")'.dependencies] | ||
| riscv = { version = "0.16.1" } | ||
| riscv = { version = "0.16.1", git = "https://github.com/JurajSadel/riscv.git", branch = "test" } |
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I opened a bunch of PRs to the riscv upstream - test branch has all PRs changes merged.
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If we're waiting on not only a bunch of PAC changes but the embedded working group, I don't see this getting merged any time soon. Let's put it back to draft, and not waste CI time on it. |
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Mostly AI-generated experiment towards #5808 - adds optional CPU and TOP power-domain power-down for light sleep on ESP32-C6 and ESP32-H2, with register retention so execution can resume after wake.
Changelog
esp-hal
TOPpower-down in light sleep, with opt-in register retention for UART, I2C and SPI.