ESP32-C6/H2: Describe the registers light-sleep retention needs

[JurajSadel]

Summary

Light-sleep TOP-domain retention in esp-hal (esp-rs/esp-hal#5874) has to back up whole register windows by name, and three areas were not described at all. Until now esp-hal reached them through hardcoded addresses, which is what this review comment asked to fix.

• SPI1 MSPI windows. SPI0 serves cache accesses and SPI1 serves CPU accesses, but both MSPI controllers implement the same permission (SPI_FMEM_PMS*/SPI_SMEM_PMS*), ECC, external-RAM timing and MMU registers; ESP-IDF's spi_mem_reg.h parameterises every one of them by controller index. The SVD only described them on SPI0, so common_patches/spi1_mspi_shared.yaml derives SPI1's copies from it. Being derived, the generated spi1.rs re-exports SPI0's types rather than duplicating them.
• The H2's L1 cache controller, which the base SVD omits entirely. It is the same block the C6 exposes as EXTMEM (242 registers at the same offsets, based at 0x600C_8000), so _cache.yml copies that peripheral and gives it the H2's CACHE name. This follows the existing esp32c5/svd/patches/_cache.yml precedent.
• PLIC_MXINT_CONF / PLIC_UXINT_CONF at offset 0x3FC. Reaching that offset also required widening both PLIC addressBlock sizes from 0x98 to 0x400; the previous size stopped at MXINT_CLAIM (0x94) and would have made the new register fall outside the block.

Only the C6 and H2 include plic.yaml and the new spi1_mspi_shared.yaml, so no other chip's generated sources change.

Test plan

• cargo xtask build ... regenerates both PACs with no further diff
• Verified against esp-hal's retention code, where the derived spans reproduce the previously hardcoded window lengths (55/41/31 words) via compile-time assertions

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