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Netlist Parsers & Writers
Netlist parsers read a netlist file into HAL's netlist representation, and netlist writers serialize a (potentially modified) netlist back out to a file. Both are implemented as plugins, which means the set of supported formats depends on which plugins your build contains — and that you can add your own format without touching the HAL core, see Creating a Netlist Parser and Creating a Netlist Writer.
You rarely call a parser or writer directly. HAL dispatches to the right one based on the file extension, both in the GUI and from the command line.
| Plugin | Extensions | Format |
|---|---|---|
verilog_parser |
.v |
Structural Verilog |
vhdl_parser |
.vhd, .vhdl
|
Structural VHDL |
Both are built by default. Note that these parse structural (gate-level, post-synthesis) netlists — a flat list of cell instances and their connections. They are not general-purpose HDL frontends and will not process behavioral RTL; that is what a synthesizer is for.
Parsing a netlist always requires a gate library, which tells HAL what the instantiated cells mean. Selecting it is the important part of an import, see Using HAL.
netlist = hal_py.NetlistFactory.load_netlist("design.v", "NangateOpenCellLibrary.hgl")If you omit the gate library, HAL tries each library it knows and keeps the first one the netlist can be instantiated with. That works surprisingly often but is slow and not always correct, so prefer naming it explicitly.
HAL's own project format (.hal) is handled separately by the netlist serializer, not by these plugins — see Using HAL.
| Plugin | Extension | Purpose |
|---|---|---|
verilog_writer |
.v |
Write the netlist back out as structural Verilog |
gexf_writer |
.gexf |
Export the netlist as a GEXF graph for external graph tools |
Both are built by default. Writing is done through the netlist writer manager, which again picks the writer by extension:
hal_py.NetlistWriterManager.write(netlist, "modified_design.v")
hal_py.NetlistWriterManager.write(netlist, "design.gexf")From the command line, a writer can be invoked directly through the options it registers; run hal -h to see which are available in your build.
The Verilog writer is what makes HAL a netlist manipulation framework rather than just a viewer. Because HAL's data model is fully writable, you can restructure a design — remove buffers, replace gates, insert or excise logic — and then export the result as a synthesizable netlist that other tools accept. This is the basis for netlist instrumentation, design patching, and hardware Trojan insertion studies, see HAL in Academia.
The GEXF writer serves a different purpose: it hands the netlist to general-purpose graph software (Gephi and similar) when you want visualizations or graph metrics that HAL's own graph algorithms plugin does not provide.
Parsers and writers register themselves with HAL when their plugin is loaded, so the file dialog in the GUI only offers formats for which a plugin is present. If a format you expect is missing, the corresponding plugin was probably not built, see Building HAL.
- Gate Library Parsers & Writers — the equivalent for gate library files
- Creating a Netlist Parser / Creating a Netlist Writer — adding your own format
- Netlist — the representation these plugins produce and consume