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Logic Evaluator

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julianspeith edited this page Sep 29, 2026 · 7 revisions

The logic evaluator is aimed to help the understanding of netlists or part of the netlists where only combinatorical logic is involved. The focus of the tool is to provide a user friendly handle to test the logic with various input combinations and to visualize the results. It will also try to detect module pingroups at input or output as well as gate pingroups at output.

Prerequisites and installation

The plugin is part of the HAL source tree but is not built by default. Enable it by passing -DPL_LOGIC_EVALUATOR=ON (or -DBUILD_ALL_PLUGINS=ON) to CMake. It requires Qt6 and the netlist_simulator_controller plugin. For on-demand compilation (see Compiled vs evaluated) a gcc compiler is required in search path.

Launch logic evaluator

The logic evaluator can be launched from the graphical view context menu (right click) after having selected the gates or modules to be analyzed: in the "Plugin actions:" section of the context menu, open the logic_evaluator submenu and choose "Launch logic evaluator...". The entry is only shown if at least one gate or module is selected. The selected combinatoric gates and combinatoric gates comprised by selected modules will be considered as subnet. The output signals of this subnet will be generated by evaluating the boolean functions on given input.

Gates must not carry the ff, latch, or ram property in order to qualify for evaluation. For all other gates it is the responsibility of the user to make sure the logic is well defined by having a valid boolean function assigned to each relevant output in associated gate library.

The logic evaluator can also be launched from the Plugins menu of the main window by choosing logic_evaluator and pressing "Launch" in the settings dialog. The current selection is used as described above. If nothing is selected, nothing happens. If gates or modules are selected but none of the gates qualifies for evaluation, a tree view will open to select the gates to be evaluated (see Relaunch). Note that the "Skip compilation" option in this settings dialog currently has no effect; to skip compilation use the "Compile selected logic" checkbox of the gate selection dialog.

Since the Logic Evaluator acts as a modeless dialog the user can continue to work with HAL while the Logic Evaluator widget is open. Obviously it is not advised to delete nets or gates which are part of the evaluation. However, while running the Logic Evaluator does not care about modules as they get only accessed at launch time.

It is safe to run multiple Logic Evaluators at the same time.

Logic evaluator controls

  • Each single input net is represented by a checkbox. By default all input signals are set to zero indicated by blue checkbox. Click a box to toggle the input.
  • Input groups have an additional spinbox. Enter a hex value into the spinbox or use small buttons to increase or decrease the value. Output groups show their value as hex number.
  • Groups are formed from module pingroups (2 to 31 pins) if all connected nets are part of the evaluated subnet and are either all inputs or all outputs. Gate pingroups (2 to 31 pins) are only used for outputs, i.e., if all pins are output pins whose nets are outputs of the subnet.
  • Menu Entry 'Options'
    • The checkbox "Run compiled logic" controls whether evaluation is done by compiled bitcode or by running BooleanLogic::eval() for each output pin (see below).
    • The checkbox "Show in graphic view" controls whether the results of the evaluation are indicated by grouping colors in the graphical netlist view.
  • Menu 'Launch'
    • Entry 'Relaunch' launches a tree view to select gates for another logic evaluator.
    • Entry 'Truth Table' launches a truth table to evaluate all possible input combinations.

Relaunch

The 'Relaunch' allows to select a new set of gates to launch another logic evaluator. The tree view shows all gates of the netlist as they are organized in modules. However, only eligible gates have a checkbox in front of them. The user can also toggle the checkbox in front of a module to select or deselect all gates from this module.

Underneath the tree view the standard HAL Searchbar widget can be used to filter gates shown in tree view. Gates might still be selected even when not shown because of filter setting. If only gates passing the filter should be part of the evaluation it is recommended to clear the selection first by removing the check marker in front of the top_module.

The checkbox "Compile selected logic" underneath the search bar controls whether the new logic evaluator compiles the logic (default) or starts in pure evaluation mode.

Truth table

The 'Truth Table' lists the output signals for all possible input combinations. It is computed using the compiled logic, so it is only available if the logic has been compiled successfully; if no compiled logic is available (compilation skipped or failed) the menu entry does nothing. Furthermore, a truth table can only be generated for at most 10 input bits; for more inputs a warning is written to the log instead. The table values be visualized by digits (0/1), letters (L/H), or color (blue/red). It is possible to sort the table by either clicking on a signal or defining up to 5 signals as sort keys. Double click on a column header (single combination) closes the truth table and puts this combination into the logic evaluator.

Compiled vs evaluated

At this point of time we have no experience concerning the performance when evaluating large netlists. When run in compiled mode the tool will try to create a sequential Ansi-C code, compile this code and load the bitcode as a temporary shared library. The tool will be set into pure evaluation mode where all output pins gets evaluated using the HAL function BooleanLogic::eval() if

  • Compilation was omitted when launching the tool (checkbox "Compile selected logic" unchecked)
  • The checkbox "Run compiled logic" in menu 'Options' gets unchecked
  • Compilation or loading of shared library failed

Graphical visualization of results

By checking "Show in graphic view" the states of all evaluated nets are shown by grouping colors. That works best if all selections have been cleared.

See also

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