fix(lsq): exclude read prefetches from TLB store permission

includes/drac_pkg.sv

@@ -923,6 +923,8 @@ typedef struct packed {
     logic simd_out_of_checkpoints;      // SIMD Rename out of checkpoints
     logic fp_out_of_checkpoints;        // FP Rename out of checkpoints
     logic empty_free_list;              // Free list out of registers
+    logic simd_empty_free_list;         // SIMD free list out of registers
+    logic fp_empty_free_list;           // FP free list out of registers
     logic is_branch;                    // Rename instruction is a branch
 } ir_cu_t;      // Rename to Control Unit
 

rtl/control_unit/rtl/control_unit.sv

@@ -421,7 +421,7 @@ module control_unit
             pipeline_flush_o.flush_ir  = 1'b0;
             pipeline_flush_o.flush_rr  = 1'b1;
             pipeline_flush_o.flush_exe = 1'b0;
-        end else if (ir_cu_i.empty_free_list) begin
+        end else if (ir_cu_i.empty_free_list || ir_cu_i.simd_empty_free_list || ir_cu_i.fp_empty_free_list) begin
             pipeline_flush_o.flush_ir  = 1'b0;
             pipeline_flush_o.flush_rr  = 1'b0;
             pipeline_flush_o.flush_exe = 1'b0;
@@ -487,7 +487,7 @@ module control_unit
             pipeline_ctrl_o.stall_ir  = 1'b1;
             pipeline_ctrl_o.stall_rr  = 1'b1;
             pipeline_ctrl_o.stall_exe = 1'b0;
-        end else if (ir_cu_i.empty_free_list) begin
+        end else if (ir_cu_i.empty_free_list || ir_cu_i.simd_empty_free_list || ir_cu_i.fp_empty_free_list) begin
             pipeline_ctrl_o.stall_iq  = 1'b1;
             pipeline_ctrl_o.stall_ir  = 1'b0;
             pipeline_ctrl_o.stall_rr  = 1'b0;

rtl/datapath/rtl/datapath.sv

@@ -616,10 +616,11 @@ assign debug_reg_o.rnm_read_resp = stage_no_stall_rr_q.prs1;
         .new_register_o         (simd_free_register_to_rename),
         .checkpoint_o           (simd_checkpoint_free_list),
         .out_of_checkpoints_o   (simd_out_of_checkpoints_free_list),
-        .empty_o                (simd_free_list_empty) // TODO not connected
+        .empty_o                (simd_free_list_empty)
     );
     `else
     assign simd_free_register_to_rename = 'h0;
+    assign simd_free_list_empty = 1'b0;
     `endif
 
     free_list #(
@@ -640,7 +641,7 @@ assign debug_reg_o.rnm_read_resp = stage_no_stall_rr_q.prs1;
         .new_register_o         (fp_free_register_to_rename),
         .checkpoint_o           (fp_checkpoint_free_list),
         .out_of_checkpoints_o   (fp_out_of_checkpoints_free_list),
-        .empty_o                (fp_free_list_empty) // TODO not connected
+        .empty_o                (fp_free_list_empty)
     );
 
     // Rename Table
@@ -768,6 +769,8 @@ assign debug_reg_o.rnm_read_resp = stage_no_stall_rr_q.prs1;
     // Signals for Control Unit
     assign ir_cu_int.valid                   = stage_iq_ir_q.instr.valid;
     assign ir_cu_int.empty_free_list         = free_list_empty;
+    assign ir_cu_int.simd_empty_free_list    = simd_free_list_empty;
+    assign ir_cu_int.fp_empty_free_list      = fp_free_list_empty;
     assign ir_cu_int.out_of_checkpoints      = out_of_checkpoints_rename;
     assign ir_cu_int.simd_out_of_checkpoints = simd_out_of_checkpoints_rename;
     assign ir_cu_int.fp_out_of_checkpoints   = fp_out_of_checkpoints_rename;

rtl/datapath/rtl/exe_stage/rtl/load_store_queue.sv

@@ -373,7 +373,7 @@ assign dtlb_comm_o.req.passthrough = 1'b0;
 assign dtlb_comm_o.req.instruction = 1'b0;
 assign dtlb_comm_o.req.asid = '0;
 assign dtlb_comm_o.req.vmid = '0;
-assign dtlb_comm_o.req.store = instr_to_translate.is_amo_store_or_cmo; // TODO: Check this, might not be exactly right...
+assign dtlb_comm_o.req.store = instr_to_translate.is_store | instr_to_translate.is_amo | instr_to_translate.is_cmo | (instr_to_translate.instr.instr_type == CMO_PREFETCH_W);
 
 assign empty_int = (num_to_exe == '0) && st_buff_empty && (num_to_translate == '0);
 `ifdef SARG_BYPASS_LSQ