fix(lsq): exclude read prefetches from TLB store permission#28
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AdeshDeshmukh wants to merge 2 commits into
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fix(lsq): exclude read prefetches from TLB store permission#28AdeshDeshmukh wants to merge 2 commits into
AdeshDeshmukh wants to merge 2 commits into
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The SIMD and FP free_list instances had their empty_o signals declared but left unconnected (datapath.sv:619,643). When these free lists are empty, new_register_o returns 'h0 (register v0/f0). Unlike scalar x0, v0 and f0 are not hardwired to zero, causing silent data corruption under heavy vector or floating-point register pressure. This patch wires the signals to the control unit to stall the IQ, matching the existing scalar free_list pattern.
CMO_PREFETCH_R and CMO_PREFETCH_I are read-only hints and should not request store permission from the TLB. CMO_PREFETCH_W correctly retains store permission as it hints at a future write.
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Closes #9.
What: Changes the TLB req.store signal in load_store_queue.sv to distinguish read prefetches from write prefetches.
Why: The old code used is_amo_store_or_cmo which included all prefetch types as stores. Read prefetches should not request write permission from the TLB.
How: Composed the existing struct fields (is_store, is_amo, is_cmo) and added CMO_PREFETCH_W explicitly. This keeps store=1 for write prefetches while dropping it for read/instruction prefetches.
Verification:
Out of scope: