Important
AnalogForge is an active research implementation. Numeric thresholds below are preregistered targets, not achieved results. Static dashboard traces are labelled demonstrations. A measured result requires a released run manifest and native simulator artifacts.
Analog design is a constrained, multi-objective conversation with physics. AnalogForge lets a language model navigate that conversation while reserving authority for executable contracts and simulators:
natural-language intent
│
▼
AnalogSpec ──► feasibility and unit checks ──► canonical TopologyIR
│ │
▼ ▼
TestbenchContract ◄── PDKModelMap ◄── parameterized SPICE netlist
│ │
├── ngspice / Xyce ◄── bounded search ──────┤
│ random · DE · PSO · BO · qNEHVI · LLM+BO
▼
nominal candidates ──► PVT ──► Monte Carlo ──► traceable Pareto report
The agent proposes a topology, parameter vector, diagnosis, or search policy. It cannot assert that a circuit converged or met a specification. Deterministic parsers read native simulator outputs and evaluate the signed measurement contract.
- A common contract across topology and PDK. Units, directions, corners, analyses, measurement windows, constraints and failure semantics remain stable while devices and testbench details change.
- Canonical topology, explicit mapping. Fifteen versioned topologies map to SKY130, GF180MCU and IHP SG13G2 through named device roles—not opaque text substitution.
- Native-evidence contract. The ngspice/Xyce adapter validates immutable PDK receipts and pre-rendered netlists, while the current default remains a visibly labelled analytic fixture.
- Fair multi-objective protocol. Six baseline interfaces share one 500-call contract. The current qNEHVI and LLM+BO implementations are CI proxies; publication rows require BoTorch/native-SPICE implementations.
- Progressive robustness. Nominal, 27-corner PVT and 100-sample Monte Carlo evidence are distinct stages. A nominal pass is never advertised as robust yield.
Install from the committed lock and run the deterministic orchestration smoke test:
uv sync --extra test --frozen
uv run analogforge --help
uv run analogforge run --state-dir .tmp-state
uv run analogforge report smoke-ota --state-dir .tmp-state
uv run analogforge benchmark --smoke --methods random,de,pso,constrained_bo,qnehvi \
--seeds 17 --max-simulations 6 --state-dir .tmp-benchThese commands exercise analytic-fixture-v1; they are not transistor-level measurements. Native simulation is a fail-closed, explicit analogforge simulate-netlist operation requiring a pre-rendered netlist, an immutable PDK receipt, a full model dependency manifest and --execute.
Launch the read-only research workbench:
cd web
corepack enable
pnpm install --frozen-lockfile
pnpm devModels use environment-only provider configuration, and the adapters do not intentionally add credentials to run records. Tool-output redaction currently covers common bearer-token and API-key key/value forms only, so traces and screenshots still require review before release. LiteLLM currency accounting additionally requires an explicit timestamped LLM_USD_TO_CNY; the repository does not hard-code an exchange rate.
| Family | Topology A | Topology B | Topology C |
|---|---|---|---|
| Op-amp / OTA | two-stage Miller | telescopic cascode | folded cascode |
| Comparator | StrongARM | double-tail dynamic | preamplifier + latch |
| LDO | classical PMOS | flipped-voltage follower | capacitor-less |
| Reference | Brokaw | Banba/current-mode | subthreshold MOS |
| Oscillator | current-starved ring | differential ring | relaxation |
Every topology maps to SKY130, GF180MCU and SG13G2, producing 45 PDK-mapped templates. Each circuit-family/PDK pair has low-power, balanced and high-performance tiers: 45 formal optimization tasks.
| Stage | Budget / evidence | Counted success |
|---|---|---|
| Nominal search | 500 SPICE calls per task/method | convergence and every hard spec met |
| Method comparison | random, DE, PSO, constrained BO, qNEHVI, LLM+BO | paired seeds, equal call accounting |
| PVT | 27 corners where models support them | all corner-specific constraints met |
| Monte Carlo | 100 samples for final candidates | yield distribution and failure modes |
| Optional layout | folded-cascode OTA across three PDKs | DRC=0, LVS pass, PEX degradation disclosed |
| Gate | Target |
|---|---|
| Nominal simulation convergence | ≥ 98% |
| Full specification satisfaction | ≥ 90% |
| PVT all-constraint satisfaction | ≥ 80% |
| Median composite objective vs best traditional baseline | no worse than 5% under 500-call budget |
Pareto hypervolume, sample efficiency, median/IQR, 95% bootstrap confidence intervals, paired comparisons, and a complete failure taxonomy accompany primary results. Failed simulations stay in the denominator.
| Artifact | Purpose |
|---|---|
| Architecture | Typed specs, topology/PDK mapping, simulation state and artifact flow |
| Methodology | Budgets, baselines, PVT/Monte Carlo, statistics and stopping rules |
| Paper cards | 30+ status-labelled analog/optimization/LLM records |
| Deep dives | Ten detailed readings and reproduction decisions |
| Project audits | 20+ analog, simulator, PDK, data and optimization projects |
| Limitations | Explicit non-claims about models, PDKs and layout |
| Screenshot protocol | Sanitized embedded-browser evidence plan |
| Manuscript source | Generic two-column pre-results manuscript and appendix |
| Compiled pre-results paper | Eight-page main paper plus status-labelled appendix |
The v0.2-core dashboard ships with synthetic, static points to make review possible before expensive runs. The default workflow uses analytic-fixture-v1; all 45 PDK mappings are deliberately UNPINNED, and native benchmark execution rejects them until immutable receipts are installed. qNEHVI and LLM+BO are runnable CI proxies, not paper baselines. No 10k dataset, trained adapter, transistor-level benchmark, PVT/Monte Carlo result or DRC/LVS/PEX result is claimed.
Milestones: v0.1-research → v0.2-core → v0.3-benchmarks → v0.5-training → v0.9-paper → v1.0.0 only after hard gates.
AnalogForge cites actual papers, tools, models, PDKs and topology sources. An official bibliographic record verifies metadata—not a paper's claims. Unlicensed PDFs, model weights and PDK/model files are never mirrored. Code and adapters authored here are intended for Apache-2.0; original prose, figures and data cards are intended for CC BY 4.0; every third-party asset retains its own terms.
Open-model simulation is not foundry signoff, and a DRC/LVS-clean open layout is not claimed to be fabrication-ready.
@software{yan2026analogforge,
author = {Yan, Weiping},
title = {AnalogForge Agent: A SPICE-Grounded Workbench for Cross-Topology, Cross-PDK Analog Design},
year = {2026},
url = {https://github.com/appleweiping/analog-forge-agent}
}Weiping Yan · University of Minnesota Twin Cities · yan00944@umn.edu