- Open simulation is not silicon. Device models approximate behavior. No result is described as silicon-proven without fabricated measurements.
- No foundry signoff. Open DRC/LVS/PEX do not equal commercial signoff or imply manufacturability.
- Cross-PDK comparability. Node, supply, device availability and model maturity differ. Raw area, current and frequency are not pooled as if technologies were interchangeable.
- Model availability. Some open PDK releases may not expose complete statistical or corner models for every device.
unsupportedis not counted as pass. - Topology coverage. Fifteen templates cannot represent the complete analog design space. Topology selection claims apply only to the frozen candidates.
- Specification feasibility. A constraint set can be physically inconsistent. Feasibility checks are conservative and cannot prove a solution exists.
- Simulation convergence. Optimizers can exploit numerical artifacts. Independent replay, bounds and residual checks reduce but do not eliminate that risk.
- Scalar rewards. Any composite objective encodes preferences. Primary reporting retains hard constraints and per-metric Pareto vectors.
- Monte Carlo sample size. One hundred samples estimates, but does not tightly establish, rare-tail yield.
- Public-data contamination. Models may have seen common netlists, tutorials or benchmark descriptions. Provenance analysis cannot fully inspect provider pretraining.
- Layout scope. The optional folded-cascode study does not establish automatic layout generality across all families.
- License boundary. Public code does not grant redistribution rights for every PDK, model card, paper, topology or example shipped around it.
AnalogForge will publish simulator failures and negative transfer. It will not use “tapeout ready,” “production signoff,” “autonomous analog designer,” or “state of the art” without evidence matching those claims.