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clk: adi: sc846: Fix and cleanup ADSP-SC846 clock tree #145

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6489e47
clk: adi: sc846: correct driver header
qasim-ijaz Aug 4, 2026
4fc8872
clk: adi: sc846: correct PLLCLK fixed factor clock div values
qasim-ijaz Aug 5, 2026
3967c1f
clk: adi: sc846: Add PLLCLK_HALF clock and correct divider clock parents
qasim-ijaz Aug 5, 2026
e0629f2
clk: adi: sc846: check input clock lookup errors
qasim-ijaz Aug 5, 2026
074b4f7
clk: adi: sc846: remove duplicate CCLK2_1 clock
qasim-ijaz Aug 5, 2026
1bd7329
clk: adi: sc846: add CGU1 DCLK1_1 clock
qasim-ijaz Aug 5, 2026
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57 changes: 31 additions & 26 deletions drivers/clk/adi/clk-adi-sc846.c
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Original file line number Diff line number Diff line change
@@ -1,12 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2022 - Analog Devices, Inc.
* Clock support for ADI SC846 processor
*
* Written and/or maintained by Timesys Corporation
*
* Author: Greg Malysa <greg.malysa@timesys.com>
*
* Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
* (C) Copyright 2026 - Analog Devices, Inc.
*/

#include <clk.h>
Expand Down Expand Up @@ -66,8 +62,13 @@
cdu = devm_ioremap(dev, res.start, resource_size(&res));

/* Input clock configuration */
clk_get_by_name(dev, "dummy", &dummy);
clk_get_by_name(dev, "sys_clkin0", &clkin0);
ret = clk_get_by_name(dev, "dummy", &dummy);
if (ret < 0)
return ret;

ret = clk_get_by_name(dev, "sys_clkin0", &clkin0);
if (ret < 0)
return ret;

clks[ADSP_SC846_CLK_DUMMY] = &dummy;
clks[ADSP_SC846_CLK_SYS_CLKIN0] = &clkin0;
Expand All @@ -93,28 +94,33 @@
clks[ADSP_SC846_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
"cgu0_vco",
CLK_SET_RATE_PARENT,
1, 4);
1, 2);
clks[ADSP_SC846_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
"cgu1_vco",
CLK_SET_RATE_PARENT,
1, 4);

1, 2);
clks[ADSP_SC846_CLK_CGU0_PLLCLK_HALF] =
clk_register_fixed_factor(NULL, "cgu0_pllclk_half", "cgu0_pllclk",
CLK_SET_RATE_PARENT, 1, 2);
clks[ADSP_SC846_CLK_CGU1_PLLCLK_HALF] =
clk_register_fixed_factor(NULL, "cgu1_pllclk_half", "cgu1_pllclk",
CLK_SET_RATE_PARENT, 1, 2);
/* CGU0 DIV */
/* Dividers from pll output */
clks[ADSP_SC846_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
clks[ADSP_SC846_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk_half",
cgu0 + CGU_DIV, 0, 5, 0);
clks[ADSP_SC846_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
clks[ADSP_SC846_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk_half",
cgu0 + CGU_DIV, 8, 5, 0);
clks[ADSP_SC846_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
clks[ADSP_SC846_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk_half",
cgu0 + CGU_DIV, 16, 5, 0);
clks[ADSP_SC846_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
clks[ADSP_SC846_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk_half",
cgu0 + CGU_DIV, 22, 7, 0);
clks[ADSP_SC846_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
cgu0 + CGU_DIV, 5, 3, 0);
clks[ADSP_SC846_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
cgu0 + CGU_DIV, 13, 3, 0);
clks[ADSP_SC846_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv",
"cgu0_pllclk",
"cgu0_pllclk_half",
cgu0 + CGU_DIVEX, 16, 8, 0);
clks[ADSP_SC846_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel",
cgu0_s1sels, 2,
Expand All @@ -126,34 +132,30 @@
"cgu0_vco",
CLK_SET_RATE_PARENT,
1, 3);
clks[ADSP_SC846_CLK_CGU0_CCLK2_1] = clk_register_fixed_factor(NULL, "cclk2_1",
"cgu0_vco",
CLK_SET_RATE_PARENT,
1, 3);
/* DCLK1_x = VCO/5 */
clks[ADSP_SC846_CLK_CGU0_DCLK1_0] = clk_register_fixed_factor(NULL, "dclk1_0",
"cgu0_vco",
CLK_SET_RATE_PARENT,
1, 5);

/* CGU1 DIV */
clks[ADSP_SC846_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
clks[ADSP_SC846_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk_half",
cgu1 + CGU_DIV, 0, 5, 0);
clks[ADSP_SC846_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
clks[ADSP_SC846_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk_half",
cgu1 + CGU_DIV, 8, 5, 0);
clks[ADSP_SC846_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
clks[ADSP_SC846_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk_half",
cgu1 + CGU_DIV, 16, 5, 0);
clks[ADSP_SC846_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
clks[ADSP_SC846_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk_half",
cgu1 + CGU_DIV, 22, 7, 0);
clks[ADSP_SC846_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
cgu1 + CGU_DIV, 5, 3, 0);
clks[ADSP_SC846_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
cgu1 + CGU_DIV, 13, 3, 0);
clks[ADSP_SC846_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv",
"cgu1_pllclk",
"cgu1_pllclk_half",
cgu1 + CGU_DIVEX, 0, 8, 0);
clks[ADSP_SC846_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv",
"cgu1_pllclk",
"cgu1_pllclk_half",
cgu1 + CGU_DIVEX, 16, 8, 0);
clks[ADSP_SC846_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel",
cgu1_s0sels, 2,
Expand All @@ -167,6 +169,9 @@
"cgu1_vco",
CLK_SET_RATE_PARENT,
1, 3);
clks[ADSP_SC846_CLK_CGU1_DCLK1_1] =
clk_register_fixed_factor(NULL, "dclk1_1", "cgu1_vco",
CLK_SET_RATE_PARENT, 1, 5);

/* Gates to enable CGU outputs */
clks[ADSP_SC846_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
Expand Down
86 changes: 44 additions & 42 deletions include/dt-bindings/clock/adi-sc5xx-clock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -38,48 +38,50 @@
#define ADSP_SC846_CLK_CGU1_S0SEL 24
#define ADSP_SC846_CLK_CGU1_S1SEL 25
#define ADSP_SC846_CLK_CGU0_CCLK2_0 26
#define ADSP_SC846_CLK_CGU0_CCLK2_1 27
#define ADSP_SC846_CLK_CGU0_DCLK1_0 28
#define ADSP_SC846_CLK_CGU0_CCLK0 29
#define ADSP_SC846_CLK_CGU0_OCLK 30
#define ADSP_SC846_CLK_CGU0_DCLK 31
#define ADSP_SC846_CLK_CGU0_SCLK1 32
#define ADSP_SC846_CLK_CGU0_SCLK0 33
#define ADSP_SC846_CLK_CGU1_CCLK0 34
#define ADSP_SC846_CLK_CGU1_OCLK 35
#define ADSP_SC846_CLK_CGU1_DCLK 36
#define ADSP_SC846_CLK_CGU1_SCLK1 37
#define ADSP_SC846_CLK_CGU1_SCLK0 38
#define ADSP_SC846_CLK_CGU1_CCLK2 39
#define ADSP_SC846_CLK_SHARC0_SEL 40
#define ADSP_SC846_CLK_ARM0_SEL 41
#define ADSP_SC846_CLK_ARM1_SEL 42
#define ADSP_SC846_CLK_CDU_DDR_SEL 43
#define ADSP_SC846_CLK_CAN_SEL 44
#define ADSP_SC846_CLK_SPDIF_SEL 45
#define ADSP_SC846_CLK_SPI_SEL 46
#define ADSP_SC846_CLK_GIGE_SEL 47
#define ADSP_SC846_CLK_XSPI2_SEL 48
#define ADSP_SC846_CLK_LP_SEL 49
#define ADSP_SC846_CLK_XSPI_SEL 50
#define ADSP_SC846_CLK_TRACE_SEL 51
#define ADSP_SC846_CLK_PWM_SEL 52
#define ADSP_SC846_CLK_MSHC_SEL 53
#define ADSP_SC846_CLK_SHARC0 54
#define ADSP_SC846_CLK_ARM0 55
#define ADSP_SC846_CLK_ARM1 56
#define ADSP_SC846_CLK_CDU_DDR 57
#define ADSP_SC846_CLK_CAN 58
#define ADSP_SC846_CLK_SPDIF 59
#define ADSP_SC846_CLK_SPI 60
#define ADSP_SC846_CLK_GIGE 61
#define ADSP_SC846_CLK_XSPI2 62
#define ADSP_SC846_CLK_LP 63
#define ADSP_SC846_CLK_XSPI 64
#define ADSP_SC846_CLK_TRACE 65
#define ADSP_SC846_CLK_PWM 66
#define ADSP_SC846_CLK_MSHC 67
#define ADSP_SC846_CLK_END 68
#define ADSP_SC846_CLK_CGU0_DCLK1_0 27
#define ADSP_SC846_CLK_CGU0_CCLK0 28
#define ADSP_SC846_CLK_CGU0_OCLK 29
#define ADSP_SC846_CLK_CGU0_DCLK 30
#define ADSP_SC846_CLK_CGU0_SCLK1 31
#define ADSP_SC846_CLK_CGU0_SCLK0 32
#define ADSP_SC846_CLK_CGU1_CCLK0 33
#define ADSP_SC846_CLK_CGU1_OCLK 34
#define ADSP_SC846_CLK_CGU1_DCLK 35
#define ADSP_SC846_CLK_CGU1_SCLK1 36
#define ADSP_SC846_CLK_CGU1_SCLK0 37
#define ADSP_SC846_CLK_CGU1_CCLK2 38
#define ADSP_SC846_CLK_SHARC0_SEL 39
#define ADSP_SC846_CLK_ARM0_SEL 40
#define ADSP_SC846_CLK_ARM1_SEL 41
#define ADSP_SC846_CLK_CDU_DDR_SEL 42
#define ADSP_SC846_CLK_CAN_SEL 43
#define ADSP_SC846_CLK_SPDIF_SEL 44
#define ADSP_SC846_CLK_SPI_SEL 45
#define ADSP_SC846_CLK_GIGE_SEL 46
#define ADSP_SC846_CLK_XSPI2_SEL 47
#define ADSP_SC846_CLK_LP_SEL 48
#define ADSP_SC846_CLK_XSPI_SEL 49
#define ADSP_SC846_CLK_TRACE_SEL 50
#define ADSP_SC846_CLK_PWM_SEL 51
#define ADSP_SC846_CLK_MSHC_SEL 52
#define ADSP_SC846_CLK_SHARC0 53
#define ADSP_SC846_CLK_ARM0 54
#define ADSP_SC846_CLK_ARM1 55
#define ADSP_SC846_CLK_CDU_DDR 56
#define ADSP_SC846_CLK_CAN 57
#define ADSP_SC846_CLK_SPDIF 58
#define ADSP_SC846_CLK_SPI 59
#define ADSP_SC846_CLK_GIGE 60
#define ADSP_SC846_CLK_XSPI2 61
#define ADSP_SC846_CLK_LP 62
#define ADSP_SC846_CLK_XSPI 63
#define ADSP_SC846_CLK_TRACE 64
#define ADSP_SC846_CLK_PWM 65
#define ADSP_SC846_CLK_MSHC 66
#define ADSP_SC846_CLK_CGU0_PLLCLK_HALF 67
#define ADSP_SC846_CLK_CGU1_PLLCLK_HALF 68
#define ADSP_SC846_CLK_CGU1_DCLK1_1 69
#define ADSP_SC846_CLK_END 70

//ADSP-SC594
#define ADSP_SC594_CLK_DUMMY 0
Expand Down