clk: adi: sc846: Fix and cleanup ADSP-SC846 clock tree - #145
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The SC846 clock driver was derived from the existing ADI clock support, but its SoC specific clock topology was implemented and is maintained by Analog Devices. Remove the stale Timesys authorship and porting annotations, and describe the file as the SC846 clock driver. Lastly update the Analog Devices copyright year from 2022 to 2026. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
The PLLCLK fixed factor clock currently divides its VCO parent rate by four. The HRM specifies that PLLCLK divides its parent rate by two. Set the PLLCLK divisor to two. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
The current driver uses the cguX_pllclk clock as parents for the divider clocks but this is incorrect because the divider clocks should have a parent which divides the rate of pllclk by 2 according to the HRM. To account for this introduce a fixed factor clock cguX_pllclk_half which does that and make that the parent of the divider clocks. As part of this add the needed clock binding IDs: ADSP_SC846_CLK_CGU0_PLLCLK_HALF and ADSP_SC846_CLK_CGU1_PLLCLK_HALF. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
Check the return values from clk_get_by_name() when obtaining the dummy and sys_clkin0 input clocks. Return the lookup error instead of continuing with invalid clock handles. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
CCLK2_1 is registered twice also it is a CGU1 clock not a CGU0 clock. Remove the incorrect CGU0 registration so CCLK2_1. Also remove the unused clock binding and renumber the remaining SC846 clock IDs. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
The driver registers the CGU0 DCLK1_0 fixed factor clock but is missing the corresponding DCLK1_1 clock from CGU1. Add DCLK1_1 as a fixed factor clock derived directly from the CGU1 VCO with a mult and div value of 1 and 5. Signed-off-by: Qasim Ijaz <Qasim.Ijaz@analog.com>
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Another small thing i noticed is that pwm_sels references clkpwm which is not a registered clock, I decided to keep it in there for now (we could make it into a dummy clock i guess but no point imo, since no one uses it) I think we would need to further develop out the clock driver to support clkpwm because it looks like its related to the frac-n-pll which we don't support atm. Edit: Pre clock changes Uboot Post clock changes Uboot |
LLM reviewThis series fixes the ADI SC846 clock driver: corrects the PLLCLK divisor, adds a run: 31021481969 Verification dataNo public SC846 HRM exists yet (not on the ADI doctools sitemap), so the clock Using Also checked: the dt-bindings renumbering in Build
CI warnings
Notes
No functional issues found; no fixup patches are proposed for this range. Install instructionsThe following one-liner installs the script if not present already: curl -fSsL "https://raw.githubusercontent.com/analogdevicesinc/doctools/refs/heads/main/ci/scripts/apply-patches.sh" -o ~/.local/bin/apply-patches.sh && grep -q "/apply-patches.sh" ~/.bashrc || echo "source ~/.local/bin/apply-patches.sh" >> $_ ; . $_More information at AI Usage. |
qasim-ijaz
changed the title
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@qasim-ijaz there should be a SC846 reference board in Edinburgh that @artursartamonovsadi is using. Note the error in the LLM review. An HRM does exist. Please update ADI doctools sitemap accordingly. |
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I have now tested this series on the ADSP-SC846, Above I have captured U-Boot clk dump output before and after the changes:
Linux also boots successfully with U-Boot built from these changes. |
@pamolloy where can i find this? |
https://github.com/analogdevicesinc/doctools https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2184x-adsp-sc84x-hrm.pdf e: you should be eligible to udpate the wiki, but idk about the analog.com |
3 participants
This PR introduces a few changes to correct the ADSP-SC846 U-Boot clock driver. The driver had a few issues with the clock tree being incorrect (some parent clocks were wrong, some clocks were not even registered, duplicate clock registrations exist, etc.). The changes also include some small fixes like return value checks, cleaning up the clock driver header and basically aligning it a bit more with the Linux clock driver . I have compiled the changes, but hardware testing is still needed (since I don't have a SC846 board right now).
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