August 2022 – Present
I am a B.Tech. Electronics and Communication Graduate (2021) with an enduring fascination about chip design and how hardware architecture inside a mobile phone actually works. After graduation, I prepared for GATE (2021-2023, 2025). In October 2022, completed an 8-week online training on VLSI Design by Internshala Trainings, during GATE preparation. Gained hands-on experience with Verilog HDL, basic RTL Design, and designed digital circuits using Xilinx Vivado 2018.1.
In October 2025, I transitioned fully into RTL design, FPGA implementation, and hardware design. Hands-on experience in Verilog testbench, VHDL & Verilog RTL design-to-bitstream flow, timing analysis, power analysis, and implementation on Cmod Artix-7 35T (xc7a35tcpg236-1) FPGA board using Xilinx Vivado 2024.1. Currently, designing an FSM-based synthesizable UART controller in Verilog from scratch and implementing on Cmod A7-35T FPGA board using Xilinx Vivado 2024.1 and Teraterm.
In this repository, each directory is divided into two sub-directories — VHDL Projects and Verilog Projects. It is organized as follows:
- Learning Lab: Designed foundational syntax tests and basic projects with a few FPGA implementations from training, but programmed from scratch.
- Skill Development: Designing intermediate or advance level projects with FPGA implementations from scratch, tutorial, or training.
- Personal Projects: Personal FPGA and RTL Design projects with FPGA implementation.