EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation
linux makefile systemverilog bash-script verilog-hdl yosys asic-verification openroad asic-design rtl-design fpga-prototyping rtl-verification rtl-to-gdsii sky130-pdk
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Updated
Jul 5, 2026 - SystemVerilog