Xilinx mlir-aie General · Discussions · GitHub

Experimental Object FIFO lowering to packet-switched stream connections
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Retiring aiex.npu.dma_memcpy_nd: converge on task-based DMA syntax

xhmelon started Aug 5, 2026 in General

5
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Using AXI4-stream interconnect to communicate bypassing DMA

aujee started Jul 21, 2026 in General · Closed

3
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taplib can't express dynamic shapes — represent access patterns in the compiler

hunhoffe started Jun 29, 2026 in General

0
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Difficult to get started

cqh963852 started Dec 21, 2025 in General

1
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Insights into DMA programming generated from Object FIFOs

AndraBisca started Dec 2, 2025 in General

1
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[RFC] Development and Release process

stephenneuendorffer started Mar 1, 2024 in General

0