Using AXI4-stream interconnect to communicate bypassing DMA

[aujee]

Hi,

While reading the AIE-ML documentation, I came across the following sections:

https://docs.amd.com/r/en-US/ug1603-ai-engine-ml-kernel-graph/Data-Communication-via-AXI4-Stream-Interconnect
https://docs.amd.com/r/en-US/am020-versal-aie-ml/AIE-ML-Tile-to-AIE-ML-Tile-Data-Communication-via-AXI4-Stream-Interconnect

My understanding is that, in some cases, core tiles can communicate directly over the AXI4-Stream interconnect bypassing the DMA.

My use case is small multicast exchange between tiles in the same row and same columns. wondering whether there is a latency advantage especially when this is a case where all tiles need to synchronize before moving on to the next flow in an iteration

is this something that's on the roadmap?

[jskimko]

I've considered this before. I guess it depends on what the kernel is doing. If the kernel needs any form of reuse, i.e., non-streaming/buffered data, then going over this streaming interface will cost you DMA-handled double buffering and compute cycles for manual buffer filling; this is orthogonal to +/- multicast. My guess is that this won't be competitive, but I haven't measured it.

[jgmelber]

Hi @aujee,

From the architecture manual linked:

Direct AXI4-Stream Interface

The AIE-ML has one 32-bit input AXI4-Stream interfaces and one 32-bit output AXI4-Stream interfaces. There are no 128-bit stream interfaces and no FIFO connected to either input or output of the stream.

There is some support for Streaming in the dialect:

• GetStreamOp
• PutStreamOP

The FIFO port on the Core is the correct port for streaming input/output IIRC.

[aujee]

Hi @jgmelber

thanks for the directions. I am still at the basic IRON level and from AIEv1 (manual AM009), it probably should be the same FIFO port though there is no actual FIFO here in AIE-ML now. I may try the dialect with a multicast using packet-switched flow configuration