Hardware/Software Co-Design Projects — Everyday

A daily portfolio of complete, non-trivial hardware/software co-design projects. Each day is a self-contained accelerator: parameterized SystemVerilog RTL with a real hardware/software interface, working C or host software that configures and drives it, and a self-checking differential testbench that verifies the hardware bit-exactly against a software golden model.

Every project ships with:

• Synthesizable, parameterized RTL — at least three submodules plus a top level, elaborating cleanly at multiple parameter sets.
• A real HW/SW interface — AXI4-Lite/AXI4-Stream, memory-mapped registers, DMA, or similar — with a documented register map or protocol.
• Software that does real work — configures the device, moves data, handles completion, and computes the reference result.
• Measured results — cycle counts, throughput, latency, and a hardware-versus-software speedup, extracted from simulation rather than asserted.
• Hand-drawn diagrams — a hardware block diagram and a title banner, plus a Mermaid transaction sequence.

Verification runs under Icarus Verilog (this environment has no Verilator/Yosys); where a synthesized area report is unavailable, an analytical estimate is given instead. See each day's README for the exact toolchain and any substitutions.

Index

Day	Project	Domain	Microarchitecture	Interface	Summary
39	PCIe Completion Reorder Engine	high-speed I/O / PCIe split-transaction ordering	eight-tag allocator + request-order FIFO + tag-indexed completion store	PCIe-like request/completion/result ready-valid channels + TileLink-UL-style telemetry CSRs + sticky W1C IRQ	Hardware accepts arbitrary completion order while preserving software-visible request order and containing invalid tags. 320 results in 760 randomized-stall clocks, 0.421053 requests/clock, 143 out-of-order completions, two contained protocol errors, full eight-request occupancy, 1,289 checks, sanitizer-clean C reference, 0 mismatches; Yosys unavailable, synthesis-oriented Icarus elaboration passed.
38	GPU Tile Mask Compactor	GPU rendering / tile-work scheduling and verification	eight parallel byte popcount lanes + hierarchical count and first/last priority reduction + elastic result stage	AXI4-Stream 64-bit mask/result transport + AHB-Lite threshold/counter CSRs + sticky W1C IRQ	Firmware chooses the sparse-tile policy while hardware compacts coverage masks into scheduling metadata. 320 masks in 783 randomized-stall clocks, 0.408685 masks/clock, one-clock unstalled latency, 645 checks, sanitizer-clean C reference, 0 mismatches; Yosys unavailable, synthesis-oriented Icarus elaboration passed.
37	Coherent Snoop Filter	multicore SoC cache coherency / design verification	two-way set-associative directory with parallel tag match, sharer vectors and round-robin replacement	CHI-like ready/valid coherence request/response channels + APB4 telemetry + sticky W1C IRQ	Firmware configures and observes a hardware snoop directory aligned with current Apple and NVIDIA SoC DV roles. 320 transactions in 1,399 randomized-stall clocks, 0.228735 transactions/clock, 19 hits, 301 misses, 90 routed probes, 126 detected protocol errors, 1,607 checks, sanitizer-clean C reference, 0 mismatches; Yosys unavailable, synthesis-oriented Icarus elaboration passed.
36	Vibration Goertzel Monitor	predictive maintenance / vibration condition monitoring	four parallel programmable second-order Goertzel resonators + parallel peak selector	AXI4-Stream signed-sample ingress + Wishbone B4 coefficient/result CSRs + sticky W1C IRQ	Firmware selects mechanical fault bands while hardware evaluates them without an FFT. 260 frames / 16,640 samples in 48,376 randomized-gap clocks, 0.343972 samples/clock, 1,570 checks, sanitizer-clean C reference, 0 mismatches; Yosys unavailable, synthesis-oriented Icarus elaboration passed.
35	Genomics Minimizer Stream Engine	genomics / sequence indexing	canonical reverse-complement/hash pipeline + rolling parallel minimum window	Avalon-ST k-mer/result streams + Avalon-MM seed/counter CSRs + sticky W1C IRQ	Hardware emits strand-independent eight-k-mer minimizers while software configures the hash seed and validates the stream. 320 k-mers / 313 results in 795 randomized-stall clocks, 0.402516 k-mers/clock, sanitizer-clean C reference, 0 mismatches; Yosys unavailable, synthesis-oriented Icarus elaboration passed.
34	ML Top-K Command Engine	ML inference / deterministic class and expert selection	balanced tree reduction: 4 leaf pairs, 2 intermediate merges, 1 root merge + registered result	selected/ready MMIO command registers + 32-bit DMA reads/writes + sticky W1C completion/error IRQ	Driver-managed INT16 top-two selection for classification, Mixture-of-Experts routing and beam pruning. 3,464 START-to-IRQ cycles, 0.092379 vectors/clock, 4-clock final-read-to-result latency, and 14.894630× over a 51,595-cycle scalar baseline; 8 directed + 312 seeded-random vectors, randomized DMA stalls, sanitizer gate clean, 0 mismatches.
33	Power Telemetry Fusion Engine	sensor fusion / platform power and thermal telemetry	descriptor front end + three-stage elastic feature/product/reduction pipeline	selected/ready MMIO configuration + descriptor-driven 32-bit DMA read/write channels + sticky W1C completion/error IRQ	Firmware chooses operating limits and weights while hardware fuses voltage droop, current and temperature for every sample. 554 START-to-IRQ cycles, 0.578662 samples/clock under randomized DMA stalls, 3-cycle pipeline latency, and 27.180505× over a 15,058-cycle scalar baseline; 8 directed + 312 seeded-random vectors, sanitizer gate clean, 0 mismatches.
32	Firmware Trace Compressor	compression / resource-constrained boot, power and fault telemetry	double-buffered 8-record ping-pong staging + stateful run encoder + shared producer/consumer rings	selected/ready MMIO control and 512-entry shared input/output ring windows + sticky W1C completion IRQ	Firmware writes timestamped events while hardware overlaps ring prefetch with run encoding and emits fixed 64-bit packets. 320 records to 88 packets (45% fewer bytes), 329 busy cycles, 0.972644 records/clock, 331-cycle START-to-IRQ latency, and 22.580060× over scalar; sanitizer gate clean, 256/4 and 512/16 alternate geometries elaborate, 0 mismatches.
31	Robot Arm Kinematics Engine	robotics kinematics / wearable exoskeleton and end-effector pose	joint FIFO + wrapped absolute-heading controller + 16-iteration fixed-point CORDIC rotator + widened X/Y accumulation	40-bit SPI command/result protocol + sticky acknowledged completion IRQ	Firmware queues calibrated link lengths and relative joint angles, then hardware returns the deterministic Q24.8 end-effector pose. 1,065,360 SPI end-to-end cycles for 320 chains / 1,744 joints, 0.052632 joints/clock in the CORDIC path, 103.550-cycle mean START-to-IRQ latency and 9.942× over scalar; sanitizer gate clean, 4/8/16-joint elaborations pass, 0 mismatches.
30	SerDes Eye Margin Engine	networking / high-speed PHY link-margin validation	streaming dataflow with an 8-entry sample FIFO, threshold classifier and contiguous-open-run tracker	APB control/status + ready/valid phase/error sample stream + sticky W1C completion IRQ	Firmware-configured PCIe/Ethernet/NVLink/CXL eye scan measures the earliest widest passing phase interval without service-jitter stalls. 426 cycles for 320 points, 0.751174 samples/clock, 106.250-cycle mean first-sample-to-IRQ latency and 8.432× over scalar; sanitizer gate clean, 0 mismatches.
29	RAS Fault Graph Engine	graph analytics / datacenter RAS fault isolation	four-lane Boolean propagation array + registered frontier/reached fixed-point feedback	selected/ready MMIO graph mailbox + result/telemetry + sticky W1C completion IRQ	Hardware blast-radius analysis for BMC firmware and fault-injection campaigns. 35,380 cycles for 320 graphs, 0.009045 graphs/clock, 7.887500-cycle average doorbell-to-IRQ latency and 14.638779× over scalar; sanitizer gate clean, 0 mismatches.
28	SPDM Nonce Replay Guard	cryptography / authenticated-management anti-replay	32-entry associative nonce memory + parallel context/epoch/nonce compare + dual priority encoders + epoch-floor policy	selected/ready MMIO mailbox for metadata and 128-bit nonce + telemetry + sticky W1C completion IRQ	BMC/security-processor boundary for rejecting authenticated-but-replayed SPDM commands. 7,870 cycles for 320 stateful requests, 0.040661 requests/clock including randomized mailbox gaps, 4.709375-cycle average doorbell-to-IRQ latency and 8.418806× over scalar; replay/stale/flush/replacement cases, sanitizer gate clean, 0 mismatches.
27	SDR Preamble Correlator	SDR / burst preamble synchronization	eight signed complex SIMD lanes + balanced I/Q reduction trees + magnitude-square threshold in a three-stage elastic pipeline	selected/ready MMIO tap/threshold control and telemetry + 128-bit AXI4-Stream ingress + 64-bit result stream + sticky completion IRQ	Driver-programmable matched filter for Wi-Fi/cellular/LoRa/satellite burst acquisition. 320 candidates in 323 cycles, 0.991 candidates/clock, 3-cycle latency and 48.54× over scalar; randomized backpressure plus full-rate pass, sanitizer gate clean, 640 checks, 0 mismatches.
26	Sobel Line-Buffer Engine	image/video / streaming edge extraction	parameterized two-row line buffer + three-column shift window + parallel signed Sobel reduction and saturating magnitude	selected/ready MMIO control/telemetry + ready/valid 8-bit input/output streams + frame-last + sticky W1C completion/error IRQ	Driver-managed camera/GPU preprocessing primitive that retains overlapping 3×3 neighborhoods on chip and freezes losslessly under output backpressure. 461 cycles for 320 inputs / 252 checked outputs, 0.546638 pixels/clock, 3-cycle window-to-output latency and 17.960954x over scalar; 304 seeded random plus 16 directed corner pixels, counters/TLAST/IRQ checked, sanitizer gate clean, 0 mismatches.
25	Bit-Serial Motor Current Loop	motor control / hard-real-time phase-current regulation	four-entry command FIFO + exact signed error + eight-cycle shift/add Q8 gain + parallel overcurrent guard + saturating PWM clamp	selected/ready MMIO mailbox with doorbell, configuration, telemetry and sticky W1C completion/fault IRQ	The deterministic inner loop behind a motor-control firmware stack: signed phase-current error is scaled by a compact bit-serial gain engine while an independent safety path checks overcurrent, then a saturator emits a center-aligned 16-bit PWM command or fault-safe zero. 13-cycle deterministic launch-to-interrupt latency, 0.076923 commands/clock, 6.668510x over scalar; 320 corner/random vectors driven through the real MMIO pins with randomized gaps, duty/flags/telemetry/IRQ checked, sanitizer gate clean, 0 mismatches.
24	USB Audio Rate Matcher	audio / USB isochronous endpoint clock-domain rate matching	Three-stage elastic pipeline: FIFO fill error, bounded Q8 proportional rate correction, and saturating PCM16 linear interpolation	Selected/ready MMIO control/telemetry + ready/valid PCM streams + frame-last + sticky completion IRQ	Bridges independent USB-host and codec clocks without hard sample slips. 740 cycles for 320 randomized/backpressured vectors, 0.432432 samples/clock, 3-cycle latency, 7.8x over a 5772-cycle scalar baseline, 0 mismatches; ASan/UBSan clean
23	DDR RAS Scrub Engine	error-correcting codes / DDR memory reliability	Parallel Hamming SECDED syndrome-reduction tree + correction stage + parameterized scrub writeback FIFO	Selected/ready MMIO descriptor and telemetry registers + 64-bit read/write DMA channels + sticky completion IRQ	Patrol scrubber reads 39-bit SECDED words, repairs single-bit faults in place, reports double-bit faults without modifying them, and drains all writebacks before interrupting firmware. 734-cycle descriptor latency, 0.414169 words/clock, 38.128× over a 27,986-cycle scalar baseline; 304 randomized/backpressured differential words, 152 repairs, 76 uncorrectable detections, 0 mismatches; ASan/UBSan clean
22	HID Touch Fusion Engine	sensor fusion / human-interface touch and force sensing	Eight parallel baseline clamps + total/right/bottom reductions feed two concurrent 32-step restoring divider engines; below-threshold frames bypass division and return the neutral centroid	SPI mode-0 command protocol (CONFIG, FRAME, STATUS, RESULT) over spi_sclk, spi_cs_n, spi_mosi, spi_miso + sticky completion IRQ	Two four-quadrant touch/force tiles fuse into pressure and a 10-bit centroid. The C stack configures calibration, moves big-endian frames, handles polling/IRQ completion, reads results, and supplies the bit-exact reference. 33.12-cycle mean launch-to-IRQ latency, 0.03019 frames/clock, 4.47× over a 148-cycle scalar baseline; 304 pin-level SPI differential frames including zero, baseline, saturation, opposing corners and full-range random inputs, 0 mismatches; ASan/UBSan clean
21	MX-Cast Custom Functional Unit (bf16 <-> MXFP4 cast on an RV32I core)	compression / block-scaled numeric format conversion (OCP Microscaling MXFP4 cast kernels for quantised LLM inference and inter-device tensor transfer)	custom functional unit tightly coupled to a three-stage RV32I pipeline (F / X / W, one retire per cycle): five combinational stateless custom-0 instructions in the execute stage beside the ALU, two bf16 per instruction because a 32-bit register holds exactly two - so the unit's width is set by the register file, not chosen. MXQ4 is the longest path: exponent subtract, one variable shift with a sticky OR of everything shifted out, then seven midpoint comparisons in parallel into a 3-bit population count - precisely what a scalar machine must serialise. Round-to-nearest-even on the non-uniform E2M1 grid needs no tie logic and no table: the pair straddling midpoint k is (k, k+1), so the even member is k for even k and k+1 for odd, which is exactly strict versus non-strict compare, and adding the sticky bit expresses 'strictly above the midpoint' without a second comparison. A single W-to-X bypass also covers load-use, so there is no load-use stall and the only bubble is the instruction fetched behind a taken branch - making cycles = instret + taken branches + 2 an exact identity checked on every job. Traps precise, priority-encoded WDOG > FETCH > ILLEGAL > ALIGN > RANGE. Both single-ported SRAMs are owned by the core while it runs and the host while it is halted, by contract rather than arbitration	MMIO register file over a selected/ready host bus with one wait state (22 registers: self-clearing START / SOFT_RST / CLR_STAT, sticky W1C DONE/TRAP interrupt, latched ERRCODE and TRAP_PC, WDOG as a retired-instruction budget, six counters - CYCLES, INSTRET, CUSTOM_OPS, BRANCH_TAKEN, LOADS, STORES - ARG0..ARG3 loaded into a0..a3 at launch, RETVAL from a0 at the halt, CAPS carrying both memory widths and the custom-instruction count, and a REGMAP_CSUM cross-checking rtl/mxq_defs.vh against sw/mxq.h) plus instruction- and data-memory windows accessible only while the core is halted, and a completion/trap interrupt	The MXFP4 cast every quantised-inference deployment runs before a tensor crosses a device boundary: 32 bf16 values become one shared E8M0 scale plus 4 bits each - 4.25 bits/element against bf16's 16. The cast is not arithmetic but bit manipulation with a hard rounding rule, which is why a scalar machine needs 46 instructions per element, 1959 per block. Five instructions absorb it - MXAMAX (amax fold with Inf/NaN clamp and subnormal flush), MXSCALE, MXQ4 (the whole quantise, sticky bit and seven parallel comparisons), MXDQ, MXPK - and deliberately not as an accelerator behind a bus: an MX cast instruction costs exactly what an ADD costs, so the kernel stays an ordinary loop whose inner iteration is four instructions instead of ninety. Both versions of each kernel, custom-0 and strictly base RV32I, are emitted from the same C file, run on the same core over the same 94 blocks, and must leave byte-identical memory - so the speedup is a measured cycle ratio between two programs, not a cost model of a machine nobody built: 11.96x quantise, 7.50x dequantise, 10.53x round trip, 194.4 cycles/block against 2324.5, 0.899 IPC, 1.531 custom instructions/element. The five instructions are ~1010 gate equivalents - 7.8% of the core's logic, a quarter of the base ALU, beside 256 kbit of SRAM. 243,523 instruction commits compared against the simulator one at a time (PC, destination register, value, address, store data of every architectural write, in order), 110,303 memory words, a full 4096-word sweep per pass against a testbench-maintained shadow - 1,357,215 checks, 0 mismatches. Five independent implementations of the cast (fixed-point model, floating-point reference, base-RV32I kernel, RTL unit, simulator) required to agree, with all 65536 bf16 values checked at 11 scales before a vector is written; 24 directed blocks including exact ties at all seven midpoints and the same ties with sticky set, 33 hand-written ISA conformance results, 7 trap programs, 300 randomised jobs; eight injected defects all caught; five geometries - 6,797,115 checks, 0 mismatches
20	Speculative-Decoding Draft-Tree Verifier (tree-based spec decode acceptance)	LLM serving / tree-based speculative decoding draft-tree verification (the acceptance step between a draft device and the target GPU)	broadcast-compare node array with a log-depth argmax reduction: the whole draft tree in MAX_NODES x 112 flops rather than a RAM, because every node is interrogated on every step - all N nodes answer par[j] == cur && accept(j) at once into a candidate mask that a ceil(log2 N)-level argmax tree reduces to a winner in the same cycle, ties breaking to the lowest index structurally (right child taken only when valid AND strictly greater, leaf i seeded with index i); the typical-acceptance floor thr[j] = max(TH_ABS, (pmax[j] * TH_REL) >> 16) precomputed by one 16x16 multiplier at load time so the walk's critical path holds no multiplier; structural validation as three parallel reductions priority-encoded NNODES > ROOT > PARENT > SELF in one cycle; the winner pushed on cycle k+1 to keep the mux out of the selection path, and CHECK gated on an empty result FIFO so a started walk can never be stalled by backpressure	APB3 control slave (21 registers: EN / IRQ_EN / 2-bit acceptance MODE / self-clearing CLR_STAT and SOFT_RST, TH_ABS and TH_REL in Q0.16, MAX_ACC clamped to MAX_DEPTH in hardware, sticky DONE/ERROR/CLAMP IRQ cleared W1C, latched ERRCODE, CAPS, ten counters with source-starve and backpressure stalls counted apart, a REGMAP_CSUM cross-checking rtl/sdv_defs.vh against sw/sdv.h, and MAX_DEPTH per-position acceptance counters; PSLVERR on unmapped addresses) + 128-bit AXI4-Stream ingress, one node record per beat {parent, draft token, target argmax, score, pmax}, TLAST ending the tree + 128-bit AXI4-Stream egress, accepted-token beats then a trailer {count, bonus token, error, (nodes << 16)	flags}; the job config is latched on the first ingress beat, so there is no doorbell write in the steady-state path
19	GPU Peer Transport Engine (RDMA-style GPU-to-GPU link)	networking / GPU-to-GPU peer interconnect transport (tensor-parallel inference collectives)	credit-based streaming dataflow: a transmit segmentation engine (2 header beats + MTU payload beats) that prefetches payload into an 8-deep staging FIFO on the header beats; a store-and-forward receiver whose RX_BUFS x MTU packet buffer pool is the credit pool, allocated and freed in order; per-QP 8-bit sequence with whole-packet discard and resync on a gap; a receive-side accumulate fold pipelined behind an 8-deep result FIFO; one shared AXI4-Lite read channel arbitrated round-robin with a grant-order tag FIFO, write channel owned by the receive path alone	work-queue / completion-queue rings in shared memory (8-word descriptors, 4-word completions) + AXI4-Lite control slave (24 registers: doorbell, ring bases, MEM_LIMIT guard, CREDIT_LIM, sequence-gap injection, 11 statistics counters with credit / link / memory stalls counted apart, CAPS, done+error IRQ cleared W1C) + pipelined AXI4-Lite memory master (separate 4-outstanding read and write channels) + 32-bit AXI4-Stream egress/ingress pair (TLAST per packet, TUSER on the header beat) + per-QP credit-return sideband	The layer underneath a collective: the thing that actually moves a tensor shard between devices while the arithmetic waits for it. Drains a work-queue ring, segments each message into MTU packets, moves them over the link under credit-based flow control, and reassembles, commits and completes them at the far end - or folds the payload into the destination instead of overwriting it, a reduce-scatter done on the wire with no kernel launched on the receiving device. A credit is a receive buffer, so nothing is dropped and there is no retransmit path; slots are freed in order, so the memory image is a function of the descriptor ring and not of bus, wire or flow-control timing - which is exactly what three passes (randomised wait states + link gaps + credit delay / full rate / one credit per queue pair) are built to break. 0.788 payload words/clock peak (88.6 % link occupancy against a 0.889 roofline set by 2 header beats per 16-word packet), 0.451 words/clock with the accumulate fold (pipelining it took that from 0.235), 29-cycle single-word message latency, 10.30x / 15.01x over scalar; bit-exact over 331 launches / 2,283 packets / 28,328 payload words per pass (31 directed: zero length, exactly MTU, MTU+1, accumulate across INT32_MAX / INT32_MIN, two accumulates onto one destination, one credit, sequence gaps on a middle and on a last packet, a 2048-word peak message, 9 rejection cases incl. error-priority ordering; plus 300 randomised), 221,952 checks incl. a full 70,656-word memory sweep, register-map checksum against the firmware header, SLVERR / recovery / IRQ-masking / W1C tests, mutation-checked with four injected defects all caught, full differential sim at MTU/QP/BUFS = 16/4/4, 32/2/4, 8/8/8, 64/4/2 - 890,883 checks, 0 mismatches
18	Kernel-DAG Scheduler (multi-GPU command processor)	heterogeneous runtime / multi-GPU kernel-DAG launch scheduling (CUDA-Graph command processor)	associative dependency scoreboard: an on-chip graph CAM whose masks are read in parallel every tick, so all MAX_NODES readiness matches resolve in one cycle; combinational affinity placer + two-level priority encoder with fixed tie-breaks; DEVICES countdown slots retiring in parallel; RUN touches no bus, and a cycle is an exact condition, not a timeout	AXI4-Lite control slave (doorbell, node/result base, seven scheduling statistics counters, per-device occupancy, done/error IRQ cleared W1C) + a pipelined AXI4-Lite memory master (4 outstanding, AR ahead of R, in-order returns)	The launch front end of a CUDA graph in hardware: a runtime has to walk the node list to answer which kernels are runnable now, and while it walks, the GPUs idle. Here a dependency CAM answers it for all 64 nodes at once, a combinational placer picks the lowest ready node and the lowest idle device its affinity mask allows, and countdown slots retire in parallel so a dependent issues the cycle its last predecessor retires. Because the graph is fetched on chip before the first decision, the schedule is a pure function of the DAG - byte-identical under randomised wait states and at full rate - and makespan == dispatched + stall + depwait and sum(dev_busy) == serial_ticks are checked on every graph. 0.985 nodes/clock peak dispatch, 32-cycle single-graph latency, 2.583x parallel compression (146,263 serial ticks in 56,632), 98.4 % AXI4-Lite occupancy in the transfer phases, 17.62x / 18.37x over scalar; bit-exact over 326 launches / 9,991 nodes per pass (17 directed shapes incl. reverse-topological labelling, pinned affinity, a 1000-tick kernel, 32-way fan-in, MAX_NODES-deep chain and MAX_NODES-wide peak; 9 rejection cases incl. two- and three-node cycles, dangling and self edges, absent device; 300 randomised relabelled DAGs), 255,388 checks incl. a full 80,844-word memory sweep, SLVERR / recovery / IRQ-masking / W1C tests, mutation-checked with three injected defects, full differential sim at 64x4, 32x2, 32x8, 128x4 - 1,113,064 checks, 0 mismatches
17	Sharded Embedding Gather-Reduce Engine (multi-GPU EmbeddingBag)	recommendation inference / sharded embedding-table gather-reduce (DLRM / TorchRec multi-GPU)	double-buffered (ping-pong) row-staging pipeline: the CHUNKS-beat burst of row i+1 overlaps the CHUNKS-cycle fold of row i exactly, LANES one-adder-deep reduce lanes, first-row init instead of a sentinel, divide-in-place MEAN through LANES 34-stage pipelined dividers (no drain FIFO)	AXI4 burst read + AXI4 burst write masters over shared device memory driven by an 8-word descriptor ring + 19-register MMIO control/statistics with a done / baglen / index / bus-error IRQ	The nn.EmbeddingBag lookup path of a multi-GPU recommender, where the sparse tower is the latency floor: per bag the engine fetches the whole index list, classifies every index against this device's shard window, gathers each local row as one CHUNKS-beat INCR burst, and folds it through LANES reduce lanes at one beat per clock. An index owned by a peer shard is skipped and counted in ST_REMOTE - that is what sizes the all-to-all, not an error - so MEAN renormalises by the locally pooled count and an all-remote bag emits the zero vector the sharded reduce expects. Because a row takes CHUNKS cycles to fold and CHUNKS beats to fetch, the ping-pong buffers match the two stages exactly; CTRL.SINGLE_BUF collapses the overlap in the same RTL and measures the gain at 1.667x. 3.374 pooled words/clock peak (87.1 % AXI occupancy, 18.97 cycles per 16-beat row), 2.917 sustained, 13.17x / 14.08x over scalar; bit-exact over 319 bags / 9,523 indices / 6,000 gathered rows / 20,416 pooled output words per pass under randomised AXI wait states, at full rate, in single-buffer mode and after injected faults (19 directed: empty bag, single local, single remote, all-remote, MAX over INT32_MIN, MIN over INT32_MAX, wrapping SUM, MEAN truncating toward zero, duplicate index, both shard boundaries, MAX_BAG peak bag, over-long bag, out-of-range index, plus 300 randomised), 248,960 checks incl. proof that nothing outside the output region is written and CSR counters cross-checked against real bus beats, SLVERR / AR-watchdog / zero-ring / IRQ W1C tests, mutation-checked, full differential sim at 64/4/64, 32/8/32, 128/4/48, 32/2/64, 0 mismatches
16	KV-Cache Paging Engine (paged-attention block table)	memory management / paged KV-cache address translation for LLM serving (heterogeneous inference)	set-associative translation cache (parallel tag compare, true-LRU move-to-front) + block-table walker FSM + LIFO physical-block allocator, one bus-done gate for lossless stalls, next-key lookahead probe	Wishbone B4 classic master over shared memory (request fetch, block-table read/write, result writeback) + MMIO control/statistics with done/out-of-memory/bus-error IRQ	The vLLM PagedAttention block table in hardware: the attention kernels want physical KV-block numbers, the runtime thinks in (sequence, logical block) pairs. A 1-cycle set-associative translation cache resolves a translation, a block-table walker handles the miss, and an unmapped entry allocates a physical block from a LIFO pool, writes the entry back and reports ALLOC; FREE returns a sequence's blocks (LIFO reuse), an exhausted pool raises a sticky out-of-memory interrupt instead of evicting on its own. The walker absorbs the next key while the current result is on the bus — 0.970 translations/clock peak (93.5 % bus occupancy), 3-cycle latency, 13.02× / 20.42× over scalar; bit-exact over 16 batches / 1,909 translations / 1,955 result words per pass under randomised memory wait states and at full rate (cold prefill, cached re-read, flush-and-rewalk, NOALLOC, eviction + LIFO reuse, OOM mid-range, bad opcode, 9-way LRU thrash, 320 randomised requests), 8,464 checks incl. the whole 2,048-word block table, Wishbone ERR_I + bus-watchdog tests, full differential sim at 16×4 / 8×2 / 32×8 / 4×4, 0 mismatches
15	GPU Vector-Search (ANN) Top-K Engine	vector search / approximate-nearest-neighbour retrieval (RAG / embedding inference)	P-lane SIMD int8 distance datapath (adder tree + int32 accumulator folding D/P beats/vector) + streaming insertion-select top-K network (K sorted slots, parallel-compare insertion, one candidate/clock)	AXI4-Stream database-vector ingress (P int8/beat) + MMIO control/status with query window, top-K readback, statistics + search-complete/error IRQ	The retrieval primitive behind RAG / embedding search (FAISS-GPU style, sharded multi-GPU): a query is loaded once, a shard streams in at P int8 elements/clock, P SIMD distance lanes score each vector (squared-L2 nearest or inner-product argmax) via an adder tree + int32 accumulator, and a streaming insertion-select network keeps the running top-K (stable tie rule) at one candidate/clock — 7.993 sustained / 8.000 peak dims/clock (P=8 roofline), 1-cycle latency, 21.80× / 25.00× over scalar; bit-exact (score and id) over 49 searches / 7,364 vectors / 58,912 beats / 762 result entries per pass under randomised ingress bubbles and at full rate (9 directed: single vector, exactly-K, fewer-than-K, planted zero-distance hit, all-identical ties, IP argmax, IP ties, int8 saturation), CSR statistics + truncated-shard error/IRQ, full differential sim at D/P/K = 64/8/8, 32/4/4, 128/16/16, 256/16/8, 0 mismatches
14	GPU All-Reduce Collective Engine (multi-GPU)	distributed training / multi-GPU collective communication (all-reduce)	R-stage × P-lane systolic reduction array (input-skewed reduce-PE chain) + descriptor-ring DMA with R-way coalesced gather + depth-R masked-scatter pipeline	descriptor-ring DMA (R-way gather + P-wide scatter) over a wide shared-memory master + MMIO control + done/error IRQ	Hardware ncclAllReduce: reduces R rank buffers of int32 element-wise (SUM/PROD/MAX/MIN) and scatters the result from a host-built descriptor ring; an R-stage × P-lane systolic array (rank r skewed r cycles) retires P elements/clock after an R-cycle fill, all frozen losslessly by one adv=mem_ready gate — 2.87 sustained / 3.97 peak words/clock (P=4 roofline), 4-cycle latency, 51.65× / 71.44× over scalar; bit-exact over 49 collectives / 3627 elements / 924 groups per pass under randomised memory wait states and at full rate (32-bit-wrapping SUM, PROD, signed MAX/MIN, tail masks, a 2048-element peak collective), CSR + zero-length-descriptor error/IRQ checks, full differential sim at R=2/4/8, 0 mismatches
13	GPU MoE Router Engine (top-k gating / dispatch)	machine-learning inference / Mixture-of-Experts routing	log-depth top-2 argmax reduction + piecewise-linear exp-LUT softmax renormalizer (two 34-stage pipelined dividers) + per-expert capacity single-cycle RMW	AXI4-Stream logit ingress + AXI4-Stream dispatch egress + AXI4-Lite control + over-capacity IRQ	Sparse-transformer expert router / MoE gate: per token selects the top-2 experts, computes a fixed-point softmax gate (257-entry exp LUT) renormalised by two 34-stage pipelined dividers, and enforces per-expert capacity with a single-cycle load RMW — 1 token/clock, 38-cycle deterministic latency, 116.94× / 131.00× over scalar; bit-exact over 316 tokens (12 directed incl. capacity storm + 300 random) under randomised bubbles + backpressure and at full rate, CSR statistics + over-capacity IRQ checks, E=4/8/16 parameterization, gate weights within 1.35e-4 of a double-precision softmax, 0 mismatches
12	Pre-Trade Risk Engine (HFT market-access gateway)	risk management / pre-trade market-access controls (HFT)	parallel heterogeneous risk-gate array + priority-encoded verdict + single-cycle position read-modify-write RAM	AXI4-Stream order ingress + AXI4-Stream decision egress + APB3 control/status + violation IRQ	Line-rate SEC 15c3-5 risk firewall: every order runs six parallel risk gates (kill, range, halt, price-band, size, notional, position, message-cap) resolved by a priority encoder to an accept/reason verdict with a same-cycle position RMW commit — 1 order/clock, 2-cycle deterministic latency, 53.39× / 53.63× over scalar; identical decisions under randomised bubbles + backpressure and at full rate, every reason code exercised, 1024-order RMW burst + kill/IRQ, 312 orders/pass, 0 mismatches
11	Feed-Integrity Engine (HFT CRC + sequence check)	error-correcting codes / market-data feed integrity (HFT)	combinational GF(2) CRC-32 fold (unrolled LFSR) + AXI4-Stream framing FSM + per-channel sequence RAM	AXI4-Stream packet ingress + AXI4-Lite control + integrity-failure IRQ	Line-rate feed-handler integrity check: a combinational CRC-32/FCS fold verifies 4 payload bytes/clock while a framing FSM + per-channel sequence RAM catch bad CRCs and dropped-packet gaps, raising a sticky IRQ — 3.77 sustained / 3.99 peak bytes/clock, 2-cycle latency, 31.02× / 31.98× over scalar; KAT-anchored (0xCBF43926), 315 packets / 27,838 bytes per pass under randomised bubbles + full rate, 37 CRC errors + 30 gaps caught, 632 records checked, 0 mismatches
10	Bit-Pack Decode Engine (HFT columnar decompression)	compression / columnar market-data decompression (HFT)	streaming bit-unpack dataflow: variable-rate bit-FIFO aligner + 4-lane barrel-shift field extractor + combinational zig-zag / 4-wide delta-prefix tail	AXI4-Stream compressed in + wide 128-bit AXI4-Stream decoded out + AXI4-Lite control + block-done/error IRQ	Line-rate columnar (FOR + delta + zig-zag + bit-pack) feed decompression: a 192-bit variable-rate bit-FIFO feeds a 4-lane barrel-shift extractor and a combinational zig-zag + 4-wide delta-prefix tail retiring up to 4 int32 values/clock at 5-cycle latency, 1.86 sustained / 4.00 peak values/clock, 20.76× / 39.85× over scalar; 268 blocks / 67,171 values / 138,438 checked decodes, 0 mismatches
9	Alpha-Signal Engine (HFT streaming signals)	quantitative finance / real-time trading signals (HFT)	deeply-pipelined fixed-point datapath + single-cycle read-modify-write per-symbol state loop + unrolled integer sqrt/divider	AXI4-Stream ticks in + AXI4-Stream signals out + AXI4-Lite control + alert IRQ	Ultra-low-latency "alpha in the wire": per-symbol fast/slow EWMA + rolling variance in a single-cycle RMW symbol RAM feed a 32-stage integer sqrt then 48-stage divider to emit a z-score / momentum / alert record every tick at a sustained 1.000 ticks/clock, 84-cycle deterministic latency, 54.73× / 83.00× over scalar; 264 streams / 57,959 ticks / 115,918 checked records, 0 mismatches
8	CAM Limit Order-Book / BBO Engine	networking / market-data (HFT)	content-addressable price-level map (associative memory) + log-depth BBO comparator trees	AXI4-Stream ingress + MMIO control/snapshot + BBO-update IRQ	Ultra-low-latency HFT book build: single-cycle parallel (side,price) match/update over 32 CAM levels, two comparator trees pick best-bid/best-ask, top of book republished 2 cycles after every message at ~1 msg/clock, 39.61× / 200.00× over scalar; 266 streams / 8,214 messages / 16,428 checked BBO records, 0 mismatches
7	CORDIC Special Function Unit (SFU)	physics kernels / transcendental math	iterative CORDIC engine (unified circular/hyperbolic) + SIMD lanes	shared submission/completion ring buffer + gather/scatter masters + IRQ	GPU SFU pool: sin/cos/exp/cosh/sinh/atan2/hypot/ln/sqrt on one shift-and-add CORDIC datapath, 4-lane SIMD, ~9 cycles/function, 34.47× / 35.58× over scalar; 264 jobs / 39,759 checked words, 0 mismatches, 1.15e-7 max error vs libm (~23 bits)
6	Philox Counter-Based RNG Engine	cryptography / Monte-Carlo RNG	fully-pipelined counter-based (Philox-4x32-10) datapath + SIMD lanes	MMIO mailbox + doorbell + IRQ, coalesced wide masked write master	GPU/cuRAND RNG core, 4-lane SIMD retires one 128-bit block/lane/clock (512 random bits/clock), 3.40 sustained / 3.71 peak draws/cycle (4.0 ideal), 441.95× / 481.76× over scalar; 294 jobs / 276,808 checked words, 0 mismatches
5	Bilinear Texture-Filter Engine	image / video processing	line-buffer window + 2×2 texel gather + Q16.16 bilinear blend	mailbox + doorbell + IRQ, coalesced wide memory master	GPU texture unit, two-row line buffer retires one filtered pixel/clock, 0.67 sustained / 0.97 peak pixels/cycle (1.0 ideal), 22.49× / 32.35× over scalar; 290 jobs / 314,316 pixels, 0 mismatches
4	Tiled Bitonic Sort Accelerator	search acceleration / sorting	pipelined Batcher bitonic sorting network (compare-exchange lane array)	MMIO + coalesced wide-DMA master + IRQ	GPU block-sort primitive, 10-stage / 80-cell network retires one 16-key (512-bit) tile/clock, 13.18 sustained keys/cycle (16.0 ideal), 105.43× / 116.20× over scalar; 286 jobs / 275,984 checked keys, 0 mismatches
3	Parallel Prefix-Sum (Scan) Engine	graph analytics / parallel primitives	parallel-prefix (Kogge-Stone) tree w/ carry chaining	APB + descriptor-driven wide DMA	GPU scan primitive, 16-lane prefix tree, 15.06 sustained words/cycle (16.0 ideal), 45.18× over scalar; 292 jobs / 257,960 checked outputs, 0 mismatches
2	Systolic GEMM Accelerator	ML inference	output-stationary systolic array	Wishbone B4	8×8 INT8 MAC array with K-accumulate tiling, up to 64 MAC/cycle, 49.35× over scalar; 273 jobs / 17,152 checked outputs, 0 mismatches
1	Streaming FIR Accelerator	DSP	streaming dataflow w/ FIFO backpressure	AXI4-Lite + AXI4-Stream	Transposed-form FIR, 8 MAC/cycle, ~1 sample/clock, 7.88× over scalar; 1354-sample differential test, 0 mismatches

Layout

dayN - <project_name>/
├── README.md          project write-up (problem, partition, architecture, results)
├── Makefile           make sw | sim | metrics | elab | synth | formal | all
├── docs/              banner.svg, block_diagram.svg, waveform.svg
├── rtl/               synthesizable sources
├── tb/                testbench + golden vectors
├── sw/                firmware / driver / host application + reference
├── scripts/           build, metric extraction, diagram generation
└── results/           metrics.md (committed) + sim.log/vcd (generated)

License

MIT — see LICENSE.